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| h8/3867 series h8/3867 hd6473867, hd6433867 h8/3866 HD6433866 h8/3865 hd6433865 h8/3864 hd6433864 h8/3863 hd6433863 h8/3862 hd6433862 h8/3827 series h8/3827 hd6473827, hd6433827 h8/3826 hd6433826 h8/3825 hd6433825 h8/3824 hd6433824 h8/3823 hd6433823 h8/3822 hd6433822 hardware manual ade-602-142b rev. 3 3/15/03 hitachi ltd. the revision list can be viewed directly by clicking the title page. the revision list summarizes the locations of revisions and additions. details should always be checked by referring to the relevant text. cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. list of items revised or added for this version page item description 1 table 1.1 features / cpu change in (2) high-speed calculation specification 2 table 1.1 features / clock pulse generators change in specification 3 table 1.1 features / lcd drive power supply addition 5 figure 1.1 block diagram modification 8 table 1.2 pin functions / power source pin modification of stabilization capacitance 13 2.1.1 features change in high-speed operation 88 figure 4.2 typical connection to crystal oscillator addition of recommended value 89 figure 4.4 typical connection to ceramic oscillator addition of recommended value 91 figure 4.7 typical connection to 32.768- khz/38.4 khz crystal oscillator (subclock) addition of description 92 figure 4.9 pin connection when not using subclock modification 95 table 5.1 operating modes modification of subsleep mode/watch mode descriptions 97 table 5.2 internal state in each operating mode modification of note 4 99 5.1.1 system control registers 1. system control register 1 (syscr1) addition of notes to bits 6 to 4 100 2. system control register 2 (syscr2) modification of bit 4 contents 102 5.2 sleep mode addition of description 104 5.3.3 oscillator settling timer after stanby mode is cleared addition of description 107 5.5.2 clearing subsleep mode ? clearing by interrupt addition of description 109 5.7.1 transition to active (medium-speed) mode addition of description 147 table 8.10 port 3 pin states modification 226 table 9.13 timer g operation modes addition of description in notes 248 9.7.5 application notes addition and modification of descriptions 251 figure 10.1 sci3 block diagram modification page item description 256 10.2.5 serial mode register (smr) / bits 1 and 0 addition of description in notes 265 table 10.4 relation between n and clock addition of description in notes 266 table 10.5 maximum bit rate for each frequency (asynchronous mode) modification of notes 267 table 10.7 relation between n and clock addition of description in notes 268 10.2.9 clock stop register 1 (ckstpr1) addition of description in notes for bits 6 and 5 303 10.5 application notes addition of 9 and 10. 357 14.2 when using the internal power supply step-down circuit modification of description 360 to 362 15.2.1 power supply voltage and operating range modification of 1 to 3 363 to 368 table 15.2 dc characteristics addition and modification 369 to 370 table 15.3 control signal timing addition and modification 371 table 15.4 serial interface (sci3-1, sci3-2) timing addition of notes 372 table 15.5 a/d converter characteristics modification 373 table 15.7 ac characteristics for external segment expansion addition 376 figure 15.6 sci-3 synchronous mode input/output timing modification of notes 377 figure 15.7 segment expansion signal timing addition i preface the h8/300l series of single-chip microcomputers has the high-speed h8/300l cpu at its core, with many necessary peripheral functions on-chip. the h8/300l cpu instruction set is compatible with the h8/300 cpu. the h8/3867 series and h8/3827 series have a system-on-a-chip architecture that includes such peripheral functions as a as an lcd controller/driver, six timers, a 14-bit pwm, a two-channel serial communication interface, and an a/d converter. this allows h8/3867 series devices to be used as embedded microcomputers in systems requiring lcd display. the h8/3867 series incorporates an lcd drive power supply and step-up constant power supply (5 v), enabling a fixed 5 v voltage to be obtained independently of v cc . this manual describes the hardware of the h8/3867 series and h8/3827 series. for details on the h8/3864 series instruction set, refer to the h8/300l series programming manual. ii contents section 1 overview.......................................................................................... 1 1.1 overview.................................................................................................................... ........ 1 1.2 internal block diagram ..................................................................................................... 6 1.3 pin arrangement and functions ........................................................................................ 7 1.3.1 pin arrangement .................................................................................................. 7 1.3.2 pin functions........................................................................................................ 9 section 2 cpu.................................................................................................. 13 2.1 overview.................................................................................................................... ........ 13 2.1.1 features ................................................................................................................ 13 2.1.2 address space ...................................................................................................... 14 2.1.3 register configuration ......................................................................................... 14 2.2 register descriptions....................................................................................................... .. 1 5 2.2.1 general registers.................................................................................................. 15 2.2.2 control registers.................................................................................................. 15 2.2.3 initial register values .......................................................................................... 16 2.3 data formats................................................................................................................ ...... 17 2.3.1 data formats in general registers....................................................................... 18 2.3.2 memory data formats.......................................................................................... 19 2.4 addressing modes ............................................................................................................ .20 2.4.1 addressing modes................................................................................................ 20 2.4.2 effective address calculation.............................................................................. 22 2.5 instruction set............................................................................................................. ....... 26 2.5.1 data transfer instructions .................................................................................... 28 2.5.2 arithmetic operations .......................................................................................... 30 2.5.3 logic operations .................................................................................................. 31 2.5.4 shift operations.................................................................................................... 31 2.5.5 bit manipulations ................................................................................................. 33 2.5.6 branching instructions.......................................................................................... 37 2.5.7 system control instructions ................................................................................. 39 2.5.8 block data transfer instruction ........................................................................... 40 2.6 basic operational timing.................................................................................................. 42 2.6.1 access to on-chip memory (ram, rom) ......................................................... 42 2.6.2 access to on-chip peripheral modules ............................................................... 43 2.7 cpu states .................................................................................................................. ....... 45 2.7.1 overview .............................................................................................................. 45 2.7.2 program execution state ...................................................................................... 46 2.7.3 program halt state................................................................................................ 46 2.7.4 exception-handling state .................................................................................... 46 iii 2.8 memory map .................................................................................................................. ... 47 2.8.1 memory map........................................................................................................ 47 2.9 application notes........................................................................................................... ... 53 2.9.1 notes on data access........................................................................................... 53 2.9.2 notes on bit manipulation ................................................................................... 55 2.9.3 notes on use of the eepmov instruction .......................................................... 61 section 3 exception handling.......................................................................... 63 3.1 overview.................................................................................................................... ........ 63 3.2 reset ....................................................................................................................... ........... 63 3.2.1 overview .............................................................................................................. 63 3.2.2 reset sequence..................................................................................................... 63 3.2.3 interrupt immediately after reset ........................................................................ 65 3.3 interrupts.................................................................................................................. .......... 65 3.3.1 overview .............................................................................................................. 65 3.3.2 interrupt control registers ................................................................................... 67 3.3.3 external interrupts................................................................................................ 76 3.3.4 internal interrupts ................................................................................................. 77 3.3.5 interrupt operations.............................................................................................. 78 3.3.6 interrupt response time ...................................................................................... 83 3.4 application notes........................................................................................................... ... 84 3.4.1 notes on stack area use...................................................................................... 84 3.4.2 notes on rewriting port mode registers............................................................. 85 section 4 clock pulse generators.................................................................... 87 4.1 overview.................................................................................................................... ........ 87 4.1.1 block diagram...................................................................................................... 87 4.1.2 system clock and subclock ................................................................................. 87 4.2 system clock generator.................................................................................................... 88 4.3 subclock generator .......................................................................................................... .91 4.4 prescalers .................................................................................................................. ......... 93 4.5 note on oscillators ......................................................................................................... ... 94 section 5 power-down modes ........................................................................ 95 5.1 overview.................................................................................................................... ........ 95 5.1.1 system control registers ..................................................................................... 98 5.2 sleep mode.................................................................................................................. ...... 103 5.2.1 transition to sleep mode ..................................................................................... 103 5.2.2 clearing sleep mode ............................................................................................ 103 5.2.3 clock frequency in sleep (medium-speed) mode.............................................. 104 5.3 standby mode................................................................................................................ .... 104 5.3.1 transition to standby mode ................................................................................. 104 5.3.2 clearing standby mode........................................................................................ 104 iv 5.3.3 oscillator settling time after standby mode is cleared...................................... 105 5.3.4 standby mode transition and pin states.............................................................. 106 5.4 watch mode .................................................................................................................. .... 107 5.4.1 transition to watch mode.................................................................................... 107 5.4.2 clearing watch mode .......................................................................................... 107 5.4.3 oscillator settling time after watch mode is cleared ........................................ 107 5.5 subsleep mode ............................................................................................................... ... 108 5.5.1 transition to subsleep mode................................................................................ 108 5.5.2 clearing subsleep mode ...................................................................................... 108 5.6 subactive mode .............................................................................................................. ... 109 5.6.1 transition to subactive mode .............................................................................. 109 5.6.2 clearing subactive mode ..................................................................................... 109 5.6.3 operating frequency in subactive mode ............................................................. 109 5.7 active (medium-speed) mode.......................................................................................... 110 5.7.1 transition to active (medium-speed) mode ....................................................... 110 5.7.2 clearing active (medium-speed) mode.............................................................. 110 5.7.3 operating frequency in active (medium-speed) mode...................................... 110 5.8 direct transfer............................................................................................................. ...... 111 5.8.1 overview of direct transfer ................................................................................ 111 5.8.2 direct transition times........................................................................................ 112 5.9 module standby mode ...................................................................................................... 115 5.9.1 setting module standby mode............................................................................. 115 5.9.2 clearing module standby mode .......................................................................... 115 section 6 rom ................................................................................................117 6.1 overview.................................................................................................................... ........ 117 6.1.1 block diagram...................................................................................................... 117 6.2 h8/3867 and h8/3827 prom mode................................................................................. 118 6.2.1 setting to prom mode........................................................................................ 118 6.2.2 socket adapter pin arrangement and memory map ........................................... 118 6.3 h8/3867 and h8/3827 programming ................................................................................ 121 6.3.1 writing and verifying .......................................................................................... 121 6.3.2 programming precautions .................................................................................... 126 6.4 reliability of programmed data........................................................................................ 127 section 7 ram ................................................................................................129 7.1 overview.................................................................................................................... ........ 129 7.1.1 block diagram...................................................................................................... 129 section 8 i/o ports...........................................................................................131 8.1 overview.................................................................................................................... ........ 131 8.2 port 1...................................................................................................................... ............ 133 8.2.1 overview .............................................................................................................. 133 v 8.2.2 register configuration and description............................................................... 133 8.2.3 pin functions........................................................................................................ 138 8.2.4 pin states .............................................................................................................. 14 0 8.2.5 mos input pull-up .............................................................................................. 140 8.3 port 3...................................................................................................................... ............ 141 8.3.1 overview .............................................................................................................. 141 8.3.2 register configuration and description............................................................... 141 8.3.3 pin functions........................................................................................................ 145 8.3.4 pin states .............................................................................................................. 14 7 8.3.5 mos input pull-up .............................................................................................. 147 8.4 port 4...................................................................................................................... ............ 148 8.4.1 overview .............................................................................................................. 148 8.4.2 register configuration and description............................................................... 148 8.4.3 pin functions........................................................................................................ 149 8.4.4 pin states .............................................................................................................. 15 0 8.5 port 5...................................................................................................................... ............ 151 8.5.1 overview .............................................................................................................. 151 8.5.2 register configuration and description............................................................... 151 8.5.3 pin functions........................................................................................................ 154 8.5.4 pin states .............................................................................................................. 15 4 8.5.5 mos input pull-up .............................................................................................. 155 8.6 port 6...................................................................................................................... ............ 156 8.6.1 overview .............................................................................................................. 156 8.6.2 register configuration and description............................................................... 156 8.6.3 pin functions........................................................................................................ 158 8.6.4 pin states .............................................................................................................. 15 8 8.6.5 mos input pull-up .............................................................................................. 159 8.7 port 7...................................................................................................................... ............ 160 8.7.1 overview .............................................................................................................. 160 8.7.2 register configuration and description............................................................... 160 8.7.3 pin functions........................................................................................................ 162 8.7.4 pin states .............................................................................................................. 16 2 8.8 port 8...................................................................................................................... ............ 163 8.8.1 overview .............................................................................................................. 163 8.8.2 register configuration and description............................................................... 163 8.8.3 pin functions........................................................................................................ 165 8.8.4 pin states .............................................................................................................. 16 6 8.9 port a...................................................................................................................... ........... 167 8.9.1 overview .............................................................................................................. 167 8.9.2 register configuration and description............................................................... 167 8.9.3 pin functions........................................................................................................ 169 8.9.4 pin states .............................................................................................................. 17 0 8.10 port b ..................................................................................................................... ............ 171 vi 8.10.1 overview .............................................................................................................. 171 8.10.2 register configuration and description............................................................... 171 8.11 input/output data inversion function............................................................................... 172 8.11.1 overview .............................................................................................................. 172 8.11.2 register configuration and descriptions ............................................................. 172 8.11.3 note on modification of serial port control register.......................................... 174 section 9 timers..............................................................................................175 9.1 overview.................................................................................................................... ........ 175 9.2 timer a..................................................................................................................... ......... 177 9.2.1 overview .............................................................................................................. 177 9.2.2 register descriptions............................................................................................ 179 9.2.3 timer operation ................................................................................................... 183 9.2.4 timer a operation states..................................................................................... 184 9.3 timer c..................................................................................................................... ......... 185 9.3.1 overview .............................................................................................................. 185 9.3.2 register descriptions............................................................................................ 187 9.3.3 timer operation ................................................................................................... 191 9.3.4 timer c operation states ..................................................................................... 193 9.4 timer f ..................................................................................................................... ......... 194 9.4.1 overview .............................................................................................................. 194 9.4.2 register descriptions............................................................................................ 197 9.4.3 cpu interface ....................................................................................................... 205 9.4.4 operation .............................................................................................................. 208 9.4.5 application notes................................................................................................. 211 9.5 timer g..................................................................................................................... ......... 213 9.5.1 overview .............................................................................................................. 213 9.5.2 register descriptions............................................................................................ 216 9.5.3 noise canceler...................................................................................................... 221 9.5.4 operation .............................................................................................................. 223 9.5.5 application notes................................................................................................. 227 9.5.6 timer g application example ............................................................................. 232 9.6 watchdog timer.............................................................................................................. .. 233 9.6.1 overview .............................................................................................................. 233 9.6.2 register descriptions............................................................................................ 234 9.6.3 timer operation ................................................................................................... 238 9.6.4 watchdog timer operation states ....................................................................... 239 9.7 asynchronous event counter (aec) ................................................................................ 240 9.7.1 overview .............................................................................................................. 240 9.7.2 register descriptions............................................................................................ 242 9.7.3 operation .............................................................................................................. 247 9.7.4 asynchronous event counter operation modes.................................................. 248 9.7.5 application notes................................................................................................. 249 vii section 10 serial communication interface ......................................................251 10.1 overview................................................................................................................... ......... 251 10.1.1 features ................................................................................................................ 2 51 10.1.2 block diagram ...................................................................................................... 253 10.1.3 pin configuration .................................................................................................. 254 10.1.4 register configuration .......................................................................................... 254 10.2 register descriptions...................................................................................................... ... 255 10.2.1 receive shift register (rsr)................................................................................. 255 10.2.2 receive data register (rdr) ................................................................................ 255 10.2.3 transmit shift register (tsr)................................................................................ 256 10.2.4 transmit data register (tdr) ............................................................................... 256 10.2.5 serial mode register (smr).................................................................................. 257 10.2.6 serial control register 3 (scr3) ........................................................................... 260 10.2.7 serial status register (ssr)................................................................................... 264 10.2.8 bit rate register (brr).......................................................................................... 268 10.2.9 clock stop register 1 (ckstpr1) ........................................................................ 272 10.2.10 serial port control register (spcr).................................................................... 273 10.3 operation .................................................................................................................. ......... 275 10.3.1 overview .............................................................................................................. 275 10.3.2 operation in asynchronous mode........................................................................ 279 10.3.3 operation in synchronous mode.......................................................................... 289 10.3.4 multiprocessor communication function............................................................ 296 10.4 interrupts................................................................................................................. ........... 303 10.5 application notes.......................................................................................................... .... 304 section 11 14-bit pwm.....................................................................................309 11.1 overview................................................................................................................... ......... 309 11.1.1 features ................................................................................................................ 3 09 11.1.2 block diagram...................................................................................................... 309 11.1.3 pin configuration ................................................................................................. 310 11.1.4 register configuration ......................................................................................... 310 11.2 register descriptions...................................................................................................... ... 311 11.2.1 pwm control register (pwcr).......................................................................... 311 11.2.2 pwm data registers u and l (pwdru, pwdrl)............................................ 312 11.2.3 clock stop register 2 (ckstpr2)...................................................................... 312 11.3 operation .................................................................................................................. ......... 314 11.3.1 operation .............................................................................................................. 31 4 11.3.2 pwm operation modes........................................................................................ 315 section 12 a/d converter..................................................................................317 12.1 overview................................................................................................................... ......... 317 12.1.1 features ................................................................................................................ 3 17 12.1.2 block diagram...................................................................................................... 318 viii 12.1.3 pin configuration ................................................................................................. 319 12.1.4 register configuration ......................................................................................... 319 12.2 register descriptions...................................................................................................... ... 320 12.2.1 a/d result registers (adrrh, adrrl)........................................................... 320 12.2.2 a/d mode register (amr).................................................................................. 320 12.2.3 a/d start register (adsr).................................................................................. 322 12.2.4 clock stop register 1 (ckstpr1)...................................................................... 323 12.3 operation .................................................................................................................. ......... 324 12.3.1 a/d conversion operation................................................................................... 324 12.3.2 start of a/d conversion by external trigger input............................................. 324 12.3.3 a/d converter operation modes ......................................................................... 325 12.4 interrupts................................................................................................................. ........... 325 12.5 typical use................................................................................................................ ........ 325 12.6 application notes.......................................................................................................... .... 328 section 13 lcd controller/driver ....................................................................329 13.1 overview................................................................................................................... ......... 329 13.1.1 features ................................................................................................................ 3 29 13.1.2 block diagram...................................................................................................... 330 13.1.3 pin configuration ................................................................................................. 331 13.1.4 register configuration ......................................................................................... 331 13.2 register descriptions...................................................................................................... ... 332 13.2.1 lcd port control register (lpcr) ..................................................................... 332 13.2.2 lcd control register (lcr) ............................................................................... 334 13.2.3 lcd control register 2 (lcr2) .......................................................................... 336 13.2.4 clock stop register 2 (ckstpr2)...................................................................... 338 13.3 operation .................................................................................................................. ......... 339 13.3.1 settings up to lcd display.................................................................................. 339 13.3.2 relationship between lcd ram and display .................................................... 342 13.3.3 luminance adjustment function (v0 pin) .......................................................... 349 13.3.4 step-up constant-voltage (5 v) power supply .................................................. 350 13.3.5 low-power-consumption lcd drive system .................................................... 350 13.3.6 operation in power-down modes........................................................................ 354 13.3.7 boosting the lcd drive power supply ............................................................... 355 13.3.8 connection to hd66100....................................................................................... 356 section 14 power supply circuit.......................................................................359 14.1 overview................................................................................................................... ......... 359 14.2 when using the internal power supply step-down circuit ............................................. 359 14.3 when not using the internal power supply step-down circuit...................................... 360 section 15 electrical characteristics .................................................................361 15.1 h8/3867 series and h8/3827 series absolute maximum ratings.................................... 361 ix 15.2 h8/3867 series and h8/3827 series electrical characteristics......................................... 362 15.2.1 power supply voltage and operating range....................................................... 362 15.2.2 dc characteristics................................................................................................ 365 15.2.3 ac characteristics................................................................................................ 371 15.2.4 a/d converter characteristics ............................................................................. 374 15.2.5 lcd characteristics ............................................................................................. 376 15.3 operation timing ........................................................................................................... ... 378 15.4 output load circuit........................................................................................................ ... 382 15.5 resonator equivalent circuit ............................................................................................ 382 appendix a cpu instruction set.......................................................................383 a.1 instructions ................................................................................................................ ........ 383 a.2 operation code map.......................................................................................................... 391 a.3 number of execution states.............................................................................................. 393 appendix b internal i/o registers.....................................................................399 b.1 addresses................................................................................................................... ........ 399 b.2 functions................................................................................................................... ......... 403 appendix c i/o port block diagrams ...............................................................454 c.1 block diagrams of port 1 .................................................................................................. 45 4 c.2 block diagrams of port 3 .................................................................................................. 45 7 c.3 block diagrams of port 4 .................................................................................................. 46 4 c.4 block diagram of port 5.................................................................................................... 4 68 c.5 block diagram of port 6.................................................................................................... 4 69 c.6 block diagram of port 7.................................................................................................... 4 70 c.7 block diagrams of port 8 .................................................................................................. 47 1 c.8 block diagram of port a................................................................................................... 47 2 c.9 block diagram of port b ................................................................................................... 47 3 appendix d port states in the different processing states ...............................474 appendix e list of product codes ....................................................................475 appendix f package dimensions ......................................................................477 1 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcomputers (mcu: microcomputer unit), built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/3867 series and h8/3827 series comprise single-chip microcomputers equipped with a controller/driver. other on-chip peripheral functions include six timers, a 14-bit pulse width modulator (pwm), two serial communication interface channels, and an a/d converter. together, these functions make the h8/3864 series ideally suited for embedded applications in systems requiring low power consumption and lcd display. models in the h8/3867 and h8/3827 series are the h8/3862 and h8/3822, with on-chip 16-kbyte rom and 1- kbyte ram, the h8/3863 and h8/3823, with 24-kbyte rom and 1-kbyte ram, the h8/3864 and h8/3824, with 32-kbyte rom and 2-kbyte ram, the h8/3865 and h8/3825, with 40-kbyte rom and 2-kbyte ram, the h8/3866 and h8/3826, with 48-kbyte rom and 2-kbyte ram, and the h8/3867 and h8/3827, with 60-kbyte rom and 2-kbyte ram. the h8/3867 and h8/3827 are also available in a ztat * version with on-chip prom which can be programmed as required by the user. table 1.1 summarizes the features of the h8/3867 series and h8/3827 series. note: * ztat (zero turn around time) is a trademark of hitachi, ltd. 2 table 1.1 features item description cpu high-speed h8/300l cpu ? general-register architecture general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) ? operating speed ? max. operating speed: 3 mhz ? add/subtract: 0.67 ? (operating at 3 mhz) ? multiply/divide: 4.67 ? (operating at 3 mhz) ? can run on 32.768 khz or 38.4 khz subclock ? instruction set compatible with h8/300 cpu ? instruction length of 2 bytes or 4 bytes ? basic arithmetic operations between registers ? mov instruction for data transfer between memory and registers ? typical instructions ? multiply (8 bits 8 bits) ? divide (16 bits 8 bits) ? bit accumulator ? register-indirect designation of bit position interrupts 36 interrupt sources ? 13 external interrupt sources (irq 4 to irq 0 , wkp 7 to wkp 0 ) ? 23 internal interrupt sources clock pulse generators two on-chip clock pulse generators ? system clock pulse generator: 0.4 to 6 mhz ? subclock pulse generator: 32.768 khz, 38.4 khz power-down modes seven power-down modes ? sleep (high-speed) mode ? sleep (medium-speed) mode ? standby mode ? watch mode ? subsleep mode ? subactive mode ? active (medium-speed) mode 3 table 1.1 features (cont) item description memory large on-chip memory ? h8/3862, h8/3822: 16-kbyte rom, 1-kbyte ram ? h8/3863, h8/3823: 24-kbyte rom, 1-kbyte ram ? h8/3864, h8/3824: 32-kbyte rom, 2-kbyte ram ? h8/3865, h8/3825: 40-kbyte rom, 2-kbyte ram ? h8/3866, h8/3826: 48-kbyte rom, 2-kbyte ram ? h8/3867, h8/3827: 60-kbyte rom, 2-kbyte ram i/o ports 64 pins ? 55 i/o pins ? 9 input pins timers six on-chip timers ? timer a: 8-bit timer count-up timer with selection of eight internal clock signals divided from the system clock (? * and four clock signals divided from the watch clock ( w ) * ? asynchronous event counter: 16-bit timer ? count-up timer able to count asynchronous external events independently of the mcu's internal clocks ? timer c: 8-bit timer ? count-up/down timer with selection of seven internal clock signals or event input from external pin ? auto-reloading ? timer f: 16-bit timer ? can be used as two independent 8-bit timers ? count-up timer with selection of four internal clock signals or event input from external pin ? provision for toggle output by means of compare-match function ? timer g: 8-bit timer ? count-up timer with selection of four internal clock signals ? incorporates input capture function (built-in noise canceler) ? watchdog timer ? reset signal generated by overflow of 8-bit counter note: * see section 4, clock pulse generator, for the definition of ?and w . 4 table 1.1 features (cont) item description serial communication interface two serial communication interface channels on chip ? sci3-1: 8-bit synchronous/asynchronous serial interface incorporates multiprocessor communication function ? sci3-2: 8-bit synchronous/asynchronous serial interface incorporates multiprocessor communication function 14-bit pwm pulse-division pwm output for reduced ripple ? can be used as a 14-bit d/a converter by connecting to an external low-pass filter. a/d converter successive approximations using a resistance ladder ? 8-channel analog input pins ? conversion time: 31/?or 62/? per channel lcd controller/driver lcd controller/driver equipped with a maximum of 32 segment pins and four common pins ? choice of four duty cycles (static, 1/2, 1/3, or 1/4) ? segment pins can be switched to general-purpose port function in 8- bit units lcd drive power supply step-up constant-voltage power supply allows lcd display (h8/3867 series only) 5 table 1.1 features (cont) item specification product lineup product code mask rom version ztat version package rom/ram size hd6433862h, hd6433822h 80-pin qfp (fp-80a) rom 16 kbytes ram 1 kbyte hd6433862f, hd6433822f 80-pin qfp (fp-80b) hd6433862w, hd6433822w 80-pin tqfp (tfp-80c) hd6433863h, hd6433823h 80-pin qfp (fp-80a) rom 24 kbytes ram 1 kbyte hd6433863f, hd6433823f 80-pin qfp (fp-80b) hd6433863w, hd6433823w 80-pin tqfp (tfp-80c) hd6433864h, hd6433824h 80-pin qfp (fp-80a) rom 32 kbytes ram 2 kbytes hd6433864f, hd6433824f 80-pin qfp (fp-80b) hd6433864w, hd6433824w 80-pin tqfp (tfp-80c) hd6433865h, hd6433825h 80-pin qfp (fp-80a) rom 40 kbytes ram 2 kbytes hd6433865f, hd6433825f 80-pin qfp (fp-80b) hd6433865w, hd6433825w 80-pin tqfp (tfp-80c) HD6433866h, hd6433826h 80-pin qfp (fp-80a) rom 48 kbytes ram 2 kbytes HD6433866f, hd6433826f 80-pin qfp (fp-80b) HD6433866w, hd6433826w 80-pin tqfp (tfp-80c) hd6433867h, hd6433827h hd6473867h, hd6473827h 80-pin qfp (fp-80a) rom 60 kbytes ram 2 kbytes hd6433867f, hd6433827f hd6473867f, hd6473827f 80-pin qfp (fp-80b) hd6433867w, hd6433827w hd6473867w, hd6473827w 80-pin tqfp (tfp-80c) 6 1.2 internal block diagram figure 1.1 shows a block diagram of the h8/3867 series and h8/3827 series. p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 / irq adtrg irq irq irq reso wkp wkp wkp wkp wkp wkp wkp wkp irq res figure 1.1 block diagram 7 1.3 pin arrangement and functions 1.3.1 pin arrangement the h8/3867 series and h8/3827 series pin arrangement is shown in figures 1.2 and 1.3. p7 7 /seg24 p7 6 /seg23 p7 5 /seg22 p7 4 /seg21 p7 3 /seg20 p7 2 /seg19 p7 1 /seg18 p7 0 /seg17 p6 7 /seg16 p6 6 /seg15 p6 5 /seg14 p6 4 /seg13 p6 3 /seg12 p6 2 /seg11 p6 1 /seg10 p6 0 /seg9 p5 7 / wkp wkp wkp wkp irq res irq adtrg irq irq irq reso wkp wkp wkp wkp figure 1.2 pin arrangement (fp-80a, tfp-80c: top view) 8 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 av ss x 1 x 2 v ss osc 2 osc 1 test res irq adtrg irq irq irq reso wkp wkp wkp wkp wkp wkp irq wkp wkp figure 1.3 pin arrangement (fp-80b: top view) 9 1.3.2 pin functions table 1.2 outlines the pin functions of the h8/3864 series. table 1.2 pin functions pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions power source pins v cc cv cc 32 26 34 28 input power supply: all v cc pins should be connected to the system power supply. see section 14, power supply circuit. v ss 5 27 7 29 input ground: all v ss pins should be connected to the system power supply (0 v). av cc 73 75 input analog power supply: this is the power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. av ss 2 4 input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0v). v 0 31 33 output lcd power supply: these are the v 1 v 2 v 3 30 29 28 32 31 30 input power supply pins for the lcd controller/driver. they incorporate a power supply split-resistance, and are normally used with v 0 and v 1 shorted. clock pins osc 1 7 9 input these pins connect to a crystal or osc 2 6 8 output ceramic oscillator, or can be used to input an external clock. see section 4, clock pulse generators, for a typical connection diagram. x 1 3 5 input these pins connect to a 32.768-khz or x 2 4 6 output 38.4-khz crystal oscillator. see section 4, clock pulse generators, for a typical connection diagram. system control res reset: when this pin is driven low, the chip is reset reso reset output: outputs the cpu internal reset signal. 10 table 1.2 pin functions (cont) pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions system control test 8 10 output test pin: this pin is reserved and cannot be used. it should be connected to v ss . interrupt pins irq irq irq irq irq irq interrupt request 0 to 4: these are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge wkp wkp wakeup interrupt request 0 to 7: these are input pins for rising or falling- edge-sensitive external interrupts. timer pins tmow 10 12 output clock output: this is an output pin for waveforms generated by the timer a output circuit. aevl aevh 25 24 27 26 input asynchronous event counter event input: this is an event input pin for input to the asynchronous event counter. tmic 15 17 input timer c event input: this is an event input pin for input to the timer c counter. ud 19 21 input timer c up/down select: this pin selects up- or down-counting for the timer c counter. the counter operates as an up-counter when this pin is high, and as a down-counter when low. tmif 17 19 input timer f event input: this is an event input pin for input to the timer f counter. tmofl 11 13 output timer fl output: this is an output pin for waveforms generated by the timer fl output compare function. tmofh 12 14 output timer fh output: this is an output pin for waveforms generated by the timer fh output compare function. tmig 13 15 input timer g capture input: this is an input pin for timer g input capture. 11 table 1.2 pin functions (cont) pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions 14-bit pwm pin pwm 18 20 output 14-bit pwm output: this is an output pin for waveforms generated by the 14- bit pwm i/o ports pb 7 to pb 0 1, 80 to 74 3 to 1, 80 to 76 input port b: this is an 8-bit input port. p4 3 72 74 input port 4 (bit 3): this is a 1-bit input port. p4 2 to p4 0 71 to 69 73 to 71 i/o port 4 (bits 2 to 0): this is a 3-bit i/o port. input or output can be designated for each bit by means of port control register 4 (pcr4). pa 3 to pa 0 33 to 36 35 to 38 i/o port a: this is a 4-bit i/o port. input or output can be designated for each bit by means of port control register a (pcra). p1 7 to p1 0 17 to 10 19 to 12 i/o port 1: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 1 (pcr1). p3 7 to p3 0 25 to 18 27 to 20 i/o port 3: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 3 (pcr3). p5 7 to p5 0 44 to 37 46 to 39 i/o port 5: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 5 (pcr5). p6 7 to p6 0 52 to 45 54 to 47 i/o port 6: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 6 (pcr6). p7 7 to p7 0 60 to 53 62 to 55 i/o port 7: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 7 (pcr7). p8 7 to p8 0 68 to 61 70 to 63 i/o port 8: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 8 (pcr8). 12 table 1.2 pin functions (cont) pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions serial communi- rxd 31 22 24 input sci3-1 receive data input: this is the sci31 data input pin. cation interface txd 31 23 25 output sci3-1 transmit data output: this is the sci31 data output pin. (sci) sck 31 21 23 i/o sci3-1 clock i/o: this is the sci31 clock i/o pin. rxd 32 70 72 input sci3-2 receive data input: this is the sci32 data input pin. txd 32 71 73 output sci3-2 transmit data output: this is the sci32 data output pin. sck 32 69 71 i/o sci3-2 clock i/o: this is the sci32 clock i/o pin. a/d converter an7 to an0 1 80 to 74 3 to 1 80 to 76 input analog input channels 7 to 0: these are analog data input channels to the a/d converter adtrg a/d converter trigger input: this is the external trigger input pin to the a/d converter lcd controller/ com 4 to com 1 33 to 36 35 to 38 output lcd common output: these are the lcd common output pins. driver seg 32 to seg 1 68 to 37 70 to 39 output lcd segment output: these are the lcd segment output pins. cl1 68 70 output lcd latch clock: this is the output pin for the segment external expansion display data latch clock. cl2 67 69 output lcd shift clock: this is the output pin for the segment external expansion display data shift clock. do 66 68 output lcd serial data output: this is the output pin for segment external expansion serial display data. m 65 67 output lcd alternation signal: this is the output pin for the segment external expansion lcd alternation signal. 13 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300l cpu are listed below. ? general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers ? instruction set with 55 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct ? register indirect ? register indirect with displacement ? register indirect with post-increment or pre-decrement ? absolute address ? immediate ? program-counter relative ? memory indirect ? 64-kbyte address space ? high-speed operation ? all frequently used instructions are executed in two to four states ? high-speed arithmetic and logic operations ? 8- or 16-bit register-register add or subtract: 0.67 ?* ? 8 8-bit multiply: 4.67 ?* ? 16 ?8-bit divide: 4.67 ?* note: * these values are at ?= 3 mhz. ? low-power operation modes sleep instruction for transfer to low-power operation 14 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. see 2.8, memory map, for details of the memory map. 2.1.3 register configuration figure 2.1 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c g eneral registers (rn) c ontrol registers (cr) 753210 64 figure 2.1 cpu registers 15 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.2, sp (r7) points to the top of the stack. lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0). condition code register (ccr): this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. 16 bit 7?nterrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see section 3.3, interrupts. bit 6?ser bit (u): can be used freely by the user. bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4?ser bit (u): can be used freely by the user. bit 3?egative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. refer to the h8/300l series programming manual for the action of each instruction on the flag bits. 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. the stack pointer should be initialized by software, by the first instruction executed after a reset. 17 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. ? bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). ? all arithmetic and logic instructions except adds and subs can operate on byte data. ? the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits ?8 bits) instructions operate on word data. ? the daa and das instructions perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. 18 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2.3. 7 6 5 4 3 2 1 0 don? care data type register no. data format 70 1-bit data rnh 76543210 don? care 70 1-bit data rnl msb lsb don? care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl notation: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb don? care 70 msb lsb 15 0 upper digit lower digit don? care 70 3 4 don? care upper digit lower digit 70 3 4 figure 2.3 register data formats 19 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. the h8/300l cpu can access word data stored in memory (mov.w instruction), but the word data must always begin at an even address. if word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. the same applies to instruction codes. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack ccr: condition code register note: ignored on return * figure 2.4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored. 20 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2.1. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @ rn 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. 2. register indirect?rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement?(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even. 21 4. register indirect with post-increment or pre-decrement?rn+ or @?n: ? register indirect with post-increment @rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. ? register indirect with pre-decrement @ rn the @ rn mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address?aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate?xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative?(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is 126 to +128 bytes ( 63 to +64 words) from the current address. the displacement should be an even number. 8. memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see 3.3, interrupts, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see 2.3.2, memory data formats, for further information. 22 2.4.2 effective address calculation table 2.2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. register indirect (1) (bset, bclr, bnot, and btst instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand. 23 table 2.2 effective address calculation addressing mode and instruction format op rm 76 3 40 15 no. effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn register indirect, @rn contents (16 bits) of register indicated by rm 0 15 register indirect with displacement, @(d:16, rn) op rm rn 87 3 40 15 op rm 76 3 40 15 disp op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @ rn 2 3 4 incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 30 rn 30 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm 24 table 2.2 effective address calculation (cont) addressing mode and instruction format no. effective address calculation method effective address (ea) 5 absolute address @aa:8 operand is 1- or 2-byte immediate data @aa:16 op 87 0 15 op 0 15 imm op disp 70 15 program-counter relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs h'ff 87 0 15 0 15 abs op #xx:16 op 87 0 15 imm immediate #xx:8 8 sign extension disp 25 table 2.2 effective address calculation (cont) addressing mode and instruction format no. effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 notation: rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address abs 26 2.5 instruction set the h8/300l series can use a total of 55 instructions, which are grouped by function in table 2.3. table 2.3 instruction set function instructions number data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @ sp. pop rn is equivalent to mov.w @sp+, rn. the same applies to the machine language. 2. bcc is a conditional branch instruction in which cc represents a condition code. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. 27 notation rd general register (destination) rs general register (source) rn general register (ead), 28 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) rn, and @rn+ addressing modes are available for word data. the @aa:8 addressing mode is available for byte data only. the @ r7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ sp pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @ sp. notes: * size: operand size b: byte w: word certain precautions are required in data access. see 2.9.1, notes on data access, for details. 29 15 0 87 op rm rn mov rm rm 15 0 87 op rn abs @aa:8 sp 30 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs rs 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd rs, rd #imm compares data in a general register with data in another general register or with immediate data, and indicates the result in the ccr. word data can be compared only between two general registers. neg b 0 rd s complement (arithmetic complement) of data in a general register notes: * size: operand size b: byte w: word 31 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. table 2.6 logic operation instructions instruction size * function and b rd s complement (logical complement) of general register contents notes: * size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift * size: operand size b: byte 32 figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) notation: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes 33 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1 * size: operand size b: byte 34 table 2.8 bit-manipulation instructions (cont) instruction size * function bxor b c * size: operand size b: byte certain precautions are required in bit manipulation. see 2.9.2, notes on bit manipulation, for details. 35 15 0 87 op imm rn operand: bit no.: notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes 36 notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont) 37 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc branches to the designated address if condition cc is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c branches unconditionally to a specified address bsr branches to a subroutine at a specified address jsr branches to a subroutine at a specified address rts returns from a subroutine 38 notation: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes 39 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte returns from an exception-handling routine sleep causes a transition from active mode to a power-down mode. see section 5, power-down modes, for details. ldc b rs pc + 2 * size: operand size b: byte 40 notation: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes 2.5.8 block data transfer instruction table 2.11 describes the block data transfer instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov if r4l 0 then repeat @r5+ 1 certain precautions are required in using the eepmov instruction. see 2.9.3, notes on use of the eepmov instruction, for details. 41 notation: op: operation field 15 0 87 op op figure 2.10 block data transfer instruction code 42 2.6 basic operational timing cpu operation is synchronized by a system clock ( ) or a subclock ( sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.11 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub or figure 2.11 on-chip memory access cycle 43 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. figures 2.12 and 2.13 show the on-chip peripheral module access cycle. two-state access to on-chip peripheral modules t 1 state bus cycle t 2 state or internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub figure 2.12 on-chip peripheral module access cycle (2-state access) 44 three-state access to on-chip peripheral modules t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub or figure 2.13 on-chip peripheral module access cycle (3-state access) 45 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2.14. figure 2.15 shows the state transitions. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode active (medium speed) mode subactive mode sleep (high-speed) mode standby mode watch mode subsleep mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized note: see section 5, power-down modes, for details on the modes and their transitions. sleep (medium-speed) mode figure 2.14 cpu operation states 46 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source occurs reset occurs interrupt source occurs exception- handling complete reset occurs figure 2.15 state transitions 2.7.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. see section 5, power-down modes for details on these modes. 2.7.3 program halt state in the program halt state there are five modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. see section 5, power-down modes for details on these modes. 2.7.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see section 3.3, interrupts. 47 2.8 memory map 2.8.1 memory map the memory map of the h8/3862 and h8/3822 is shown in figure 2.16 (1), that of the h8/3863 and h8/3823 in figure 2.16 (2), that of the h8/3864 and h8/3824 in figure 2.16 (3), that of the h8/3865 and h8/3825 in figure 2.16 (4), that of the h8/3866 and h8/3826 in figure 2.16 (5), and that of the h8/3867 and h8/3827 in figure 2.16 (6). h'0000 h'0029 h'002a h'3fff h'f740 h'f75f h'f780 h'fb7f h'ff90 h'ffff interrupt vector area on-chip rom 16 kbytes (16384 bytes) 1024 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (1) h8/3862 and h8/3822 memory map 48 h'0000 h'0029 h'002a h'5fff h'f740 h'f75f h'f780 h'fb7f h'ff90 h'ffff interrupt vector area on-chip rom 24 kbytes (24576 bytes) 1024 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (2) h8/3863 and h8/3823 memory map 49 h'0000 h'0029 h'002a h'7fff h'f740 h'f75f h'f780 h'ff7f h'ff90 h'ffff interrupt vector area on-chip rom 32 kbytes (32768 bytes) 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (3) h8/3864 and h8/3824 memory map 50 h'0000 h'0029 h'002a h'9fff h'f740 h'f75f h'f780 h'ff7f h'ff90 h'ffff interrupt vector area on-chip rom 40 kbytes (40960 bytes) 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (4) h8/3865 and h8/3825 memory map 51 h'0000 h'0029 h'002a h'bfff h'f740 h'f75f h'f780 h'ff7f h'ff90 h'ffff interrupt vector area on-chip rom 48 kbytes (49152 bytes) 2048 bytes on-chip ram not used internal i/o registers (112 bytes) not used not used lcd ram (32 bytes) figure 2.16 (5) h8/3866 and h8/3826 memory map 52 h'0000 h'0029 h'002a h'edff h'f740 h'f75f h'f780 h'ff7f h'ff90 h'ffff interrupt vector area on-chip rom 60 kbytes (60928 bytes) 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (6) h8/3867 and h8/3827 memory map 53 2.9 application notes 2.9.1 notes on data access 1. access to empty areas: the address space of the h8/300l cpu includes empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. data transfer from cpu to empty area: the transferred data will be lost. this action may also cause the cpu to misoperate. data transfer from empty area to cpu: unpredictable data is transferred. 2. access to internal i/o registers: internal data transfer to or from on-chip modules other than the rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: unpredictable data will be written to lower part of cpu register. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas. figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 54 interrupt vector area (42 bytes) on-chip rom 32kbytes on-chip ram not used not used not used lcd ram (32 bytes) internal i/o registers (112 bytes) access word byte 2 2 2 * 2 h'ff90 h'ffff notes: 1. 2. * 1 the example of the h8/3864 and h8/3824 is shown here. this address is h'3fff in the h8/3862 and h8/3822 (16-kbyte on-chip rom), h'5fff in the h8/3863 and h8/3823 (24-kbyte on-chip rom), h'9fff in the h8/3865 and h8/3825 (40-kbyte on-chip rom), h'bfff in the h8/3866 and h8/3826 (48-kbyte on-chip rom), and h'edff in the h8/3867 and h8/3827 (60-kbyte on-chip rom). this address is h'fb7f in the h8/3862, h8/3822, h8/3863, and h8/3823 (1024 bytes of on-chip ram). h'ff98 to h'ff9f figure 2.17 data size and number of states for access to and from on-chip peripheral modules 55 2.9.2 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an i/o port. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address 1. bit manipulation in two registers assigned to the same address example 1: timer load register and timer counter figure 2.18 shows an example in which two timer registers share the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. order of operation operation 1 read timer counter data is read (one byte) 2 modify the cpu modifies (sets or resets) the bit designated in the instruction 3 write the altered byte data is written to the timer load register the timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. read write c ount clock timer counter timer load register reload internal bus figure 2.18 timer configuration example 56 example 2: bset instruction executed designating port 3 p3 7 and p3 6 are designated as input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins and output low-level signals. in this example, the bset instruction is used to change pin p3 0 to high-level output. [a: prior to executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00000 [b: bset instruction executed] bset #0 , @pdr3 the bset instruction is executed designating port 3. [c: after executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr3 0 0 1 11111 pdr3 0 1 0 00001 [d: explanation of how bset operates] when the bset instruction is executed, first the cpu reads port 3. since p3 7 and p3 6 are input pins, the cpu reads the pin states (low-level and high-level input). p3 5 to p3 0 are output pins, so the cpu reads the value in pdr3. in this example pdr3 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr3 data to h'41. finally, the cpu writes this value (h'41) to pdr3, completing execution of bset. as a result of this operation, bit 0 in pdr3 becomes 1, and p3 0 outputs a high-level signal. however, bits 7 and 6 of pdr3 end up with different values. to avoid this problem, store a copy of the pdr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr3. 57 [a: prior to executing bset] mov. b #80, r0l the pdr3 value (h'80) is written to a work area in memory mov. b r0l, @ram0 (ram0) as well as to pdr3 mov. b r0l, @pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00000 ram0 1 0 0 00000 [b: bset instruction executed] bset #0 , @ram0 the bset instruction is executed designating the pdr3 work area (ram0). [c: after executing bset] mov. b @ram0, r0l the work area (ram0) value is written to pdr3. mov. b r0l, @pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr3 0 0 1 11111 pdr3 1 0 0 00001 ram0 1 0 0 00001 58 2. bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 3 control register pcr3 as in the examples above, p3 7 and p3 6 are input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p3 0 to an input port. it is assumed that a high-level signal will be input to this input pin. [a: prior to executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00000 [b: bclr instruction executed] bclr #0 , @pcr3 the bclr instruction is executed designating pcr3. [c: after executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level pcr3 1 1 1 11110 pdr3 1 0 0 00000 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads pcr3. since pcr3 is a write-only register, the cpu reads a value of h'ff, even though the pcr3 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, this value (h'fe) is written to pcr3 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr3 becomes 0, making p3 0 an input port. however, bits 7 and 6 in pcr3 change to 1, so that p3 7 and p3 6 change from input pins to output pins. to avoid this problem, store a copy of the pcr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pcr3. 59 [a: prior to executing bclr] mov. b #3f, r0l the pcr3 value (h'3f) is written to a work area in memory mov. b r0l, @ram0 (ram0) as well as to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00000 ram0 0 0 1 11111 [b: bclr instruction executed] bclr #0 , @ram0 the bclr instruction is executed designating the pcr3 work area (ram0). [c: after executing bclr] mov. b @ram0, r0l the work area (ram0) value is written to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr3 0 0 1 11110 pdr3 1 0 0 00000 ram0 0 0 1 11110 60 table 2.12 lists the pairs of registers that share identical addresses. table 2.13 lists the registers that contain write-only bits. table 2.12 registers with shared addresses register name abbreviation address timer counter and timer load register c tcc/tlc h'ffb5 port data register 1 * pdr1 h'ffd4 port data register 3 * pdr3 h'ffd6 port data register 4 * pdr4 h'ffd7 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb port data register a * pdra h'ffdd note: * port data registers have the same addresses as input pins. table 2.13 registers with write-only bits register name abbreviation address port control register 1 pcr1 h'ffe4 port control register 3 pcr3 h'ffe6 port control register 4 pcr4 h'ffe7 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb port control register a pcra h'ffed timer control register f tcrf h'ffb6 pwm control register pwcr h'ffd0 pwm data register u pwdru h'ffd1 pwm data register l pwdrl h'ffd2 61 2.9.3 notes on use of the eepmov instruction ? the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. ? when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed 62 63 section 3 exception handling 3.1 overview exception handling is performed in the h8/3864 series when a reset or interrupt occurs. table 3.1 shows the priorities of these two types of exception handling. table 3.1 exception handling types and priorities priority exception source time of start of exception handling high reset exception handling starts as soon as the reset state is cleared low interrupt when an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 reset 3.2.1 overview a reset is the highest-priority exception. the internal state of the cpu and the registers of the on- chip peripheral modules are initialized. 3.2.2 reset sequence as soon as the res pin goes low, all processing is stopped and the chip enters the reset state. to make sure the chip is reset properly, observe the following precautions. ? at power on: hold the res pin low until the clock pulse generator output stabilizes. ? resetting during operation: hold the res pin low for at least 10 system clock cycles. reset exception handling takes place as follows. ? the cpu internal state and the registers of on-chip peripheral modules are initialized, with the i bit of the condition code register (ccr) set to 1. ? the pc is loaded from the reset exception handling vector address (h'0000 to h'0001), after which the program starts executing from the address indicated in pc. 64 when system power is turned on or off, the res pin should be held low. figure 3.1 shows the reset sequence starting from res input. vector fetch internal address bus internal read signal internal write signal internal data bus (16-bit) res internal processing program initial instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) first instruction of program (2) (3) (2) (1) reset cleared figure 3.1 reset sequence 65 3.2.3 interrupt immediately after reset after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.w #xx: 16, sp). 3.3 interrupts 3.3.1 overview the interrupt sources include 13 external interrupts (irq 4 to irq 0 , wkp 7 to wkp 0 ) and 23 internal interrupts from on-chip peripheral modules. table 3.2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features: ? internal and external interrupts can be masked by the i bit in ccr. when the i bit is set to 1, interrupt request flags can be set but the interrupts are not accepted. ? irq 4 to irq 0 and wkp 7 to wkp 0 can be set to either rising edge sensing or falling edge sensing. 66 table 3.2 interrupt sources and their priorities interrupt source interrupt vector number vector address priority res reset 0 h'0000 to h'0001 high irq 0 irq 0 4 h'0008 to h'0009 irq 1 irq 1 5 h'000a to h'000b irq 2 irq 2 6 h'000c to h'000d irq 3 irq 3 7 h'000e to h'000f irq 4 irq 4 8 h'0010 to h'0011 wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 9 h'0012 to h'0013 timer a timer a overflow 11 h'0016 to h'0017 asynchronous counter asynchronous counter overflow 12 h'0018 to h'0019 timer c timer c overflow or underflow 13 h'001a to h'001b timer fl timer fl compare match timer fl overflow 14 h'001c to h'001d timer fh timer fh compare match timer fh overflow 15 h'001e to h'001f timer g timer g input capture timer g overflow 16 h'0020 to h'0021 sci3-1 sci3-1 transmit end sci3-1 transmit data empty sci3-1 receive data full sci3-1 overrrun error sci3-1 framing error sci3-1 parity error 17 h'0022 to h'0023 sci3-2 sci3-2 transmit end sci3-2 transmit data empty sci3-2 receive data full sci3-2 overrun error sci3-2 framing error sci3-2 parity error 18 h'0024 to h'0025 a/d a/d conversion end 19 h'0026 to h'0027 (sleep instruction executed) direct transfer 20 h'0028 to h'0029 low note: vector addresses h'0002 to h'0007 and h'0014 to h'0015 are reserved and cannot be used. 67 3.3.2 interrupt control registers table 3.3 lists the registers that control interrupts. table 3.3 interrupt control registers name abbreviation r/w initial value address irq edge select register iegr r/w h'e0 h'fff2 interrupt enable register 1 ienr1 r/w h'00 h'fff3 interrupt enable register 2 ienr2 r/w h'00 h'fff4 interrupt request register 1 irr1 r/w * h'20 h'fff6 interrupt request register 2 irr2 r/w * h'00 h'fff7 wakeup interrupt request register iwpr r/w * h'00 h'fff9 wakeup edge select register wegr r/w h'00 h'ff90 note: * write is enabled only for writing of 0 to clear a flag. 1. irq edge select register (iegr) bit initial value read/write 7 1 6 1 5 1 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w iegr is an 8-bit read/write register used to designate whether pins irq 4 to irq 0 are set to rising edge sensing or falling edge sensing. bits 7 to 5: reserved bits bits 7 to 5 are reserved: they are always read as 1 and cannot be modified. bit 4: irq 4 edge select (ieg4) bit 4 selects the input sensing of the irq 4 pin and adtrg pin. bit 4 ieg4 description 0 falling edge of irq adtrg irq adtrg 68 bit 3: irq 3 edge select (ieg3) bit 3 selects the input sensing of the irq 3 pin and tmif pin. bit 3 ieg3 description 0 falling edge of irq irq bit 2: irq 2 edge select (ieg2) bit 2 selects the input sensing of pin irq 2 . bit 2 ieg2 description 0 falling edge of irq irq bit 1: irq 1 edge select (ieg1) bit 3 selects the input sensing of the irq 1 pin and tmic pin. bit 1 ieg1 description 0 falling edge of irq irq bit 0: irq 0 edge select (ieg0) bit 0 selects the input sensing of pin irq 0 . bit 0 ieg0 description 0 falling edge of irq irq 69 2. interrupt enable register 1 (ienr1) bit initial value read/write 7 ienta 0 r/w 6 0 r/w 5 ienwp 0 r/w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w ienr1 is an 8-bit read/write register that enables or disables interrupt requests. bit 7: timer a interrupt enable (ienta) bit 7 enables or disables timer a overflow interrupt requests. bit 7 ienta description 0 disables timer a interrupt requests (initial value) 1 enables timer a interrupt requests bit 6: reserved bit bit 6 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 5: wakeup interrupt enable (ienwp) bit 5 enables or disables wkp 7 to wkp 0 interrupt requests. bit 5 ienwp description 0 disables wkp wkp wkp wkp bits 4 to 0: irq 4 to irq 0 interrupt enable (ien4 to ien0) bits 4 to 0 enable or disable irq 4 to irq 0 interrupt requests. bit n ienn description 0 disables interrupt requests from pin irqn irqn 70 3. interrupt enable register 2 (ienr2) bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 0 r/w 4 ientg 0 r/w 3 ientfh 0 r/w 0 ienec 0 r/w 2 ientfl 0 r/w 1 ientc 0 r/w ienr2 is an 8-bit read/write register that enables or disables interrupt requests. bit 7: direct transfer interrupt enable (iendt) bit 7 enables or disables direct transfer interrupt requests. bit 7 iendt description 0 disables direct transfer interrupt requests (initial value) 1 enables direct transfer interrupt requests bit 6: a/d converter interrupt enable (ienad) bit 6 enables or disables a/d converter interrupt requests. bit 6 ienad description 0 disables a/d converter interrupt requests (initial value) 1 enables a/d converter interrupt requests bit 5: reserved bit bit 5 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 4: timer g interrupt enable (ientg) bit 4 enables or disables timer g input capture or overflow interrupt requests. bit 4 ientg description 0 disables timer g interrupt requests (initial value) 1 enables timer g interrupt requests 71 bit 3: timer fh interrupt enable (ientfh) bit 3 enables or disables timer fh compare match and overflow interrupt requests. bit 3 ientfh description 0 disables timer fh interrupt requests (initial value) 1 enables timer fh interrupt requests bit 2: timer fl interrupt enable (ientfl) bit 2 enables or disables timer fl compare match and overflow interrupt requests. bit 2 ientfl description 0 disables timer fl interrupt requests (initial value) 1 enables timer fl interrupt requests bit 1: timer c interrupt enable (ientc) bit 1 enables or disables timer c overflow and underflow interrupt requests. bit 1 ientc description 0 disables timer c interrupt requests (initial value) 1 enables timer c interrupt requests bit 0: asynchronous event counter interrupt enable (ienec) bit 0 enables or disables asynchronous event counter interrupt requests. bit 0 ienec description 0 disables asynchronous event counter interrupt requests (initial value) 1 enables asynchronous event counter interrupt requests for details of sci3-1 and sci3-2 interrupt control, see 6. serial control register 3 (scr3) in section 10.4.2. 72 4. interrupt request register 1 (irr1) bit initial value read/write 7 irrta 0 r/w 6 0 r/w 5 1 4 irri4 0 r/w 3 irri3 0 r/w 0 irri0 0 r/w 2 irri2 0 r/w 1 irri1 0 r/w ** * **** note: * only a write of 0 for flag clearing is possible irr1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer a or irq 4 to irq 0 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: timer a interrupt request flag (irrta) bit 7 irrta description 0 clearing conditions: (initial value) when irrta = 1, it is cleared by writing 0 1 setting conditions: when the timer a counter value overflows from h'ff to h'00 bit 6: reserved bit bit 6 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 5: reserved bit bit 5 is reserved; it is always read as 1 and cannot be modified. bits 4 to 0: irq 4 to irq 0 interrupt request flags (irri4 to irri0) bit n irrin description 0 clearing conditions: (initial value) when irrin = 1, it is cleared by writing 0 1 setting conditions: when pin irqn 73 5. interrupt request register 2 (irr2) bit initial value read/write 7 irrdt 0 r/w 6 irrad 0 r/w 5 0 r/w 4 irrtg 0 r/w 3 irrtfh 0 r/w 0 irrec 0 r/w 2 irrtfl 0 r/w 1 irrtc 0 r/w ** ***** note: * only a write of 0 for flag clearing is possible irr2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, a/d converter, timer g, timer fh, timer fc, or timer c interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: direct transfer interrupt request flag (irrdt) bit 7 irrdt description 0 clearing conditions: (initial value) when irrdt = 1, it is cleared by writing 0 1 setting conditions: when a direct transfer is made by executing a sleep instruction while dton = 1 in syscr2 bit 6: a/d converter interrupt request flag (irrad) bit 6 irrad description 0 clearing conditions: (initial value) when irrad = 1, it is cleared by writing 0 1 setting conditions: when a/d conversion is completed and adsf is cleared to 0 in adsr bit 5: reserved bit bit 5 is a readable/writable reserved bit. it is initialized to 0 by a reset. 74 bit 4: timer g interrupt request flag (irrtg) bit 4 irrtg description 0 clearing conditions: (initial value) when irrtg = 1, it is cleared by writing 0 1 setting conditions: when the tmig pin is designated for tmig input and the designated signal edge is input, or when tcg overflows while ovie is set to 1 in tmg bit 3: timer fh interrupt request flag (irrtfh) bit 3 irrtfh description 0 clearing conditions: (initial value) when irrtfh = 1, it is cleared by writing 0 1 setting conditions: when tcfh and ocrfh match in 8-bit timer mode, or when tcf (tcfl, tcfh) and ocrf (ocrfl, ocrfh) match in 16-bit timer mode bit 2: timer fl interrupt request flag (irrtfl) bit 2 irrtfl description 0 clearing conditions: (initial value) when irrtfl= 1, it is cleared by writing 0 1 setting conditions: when tcfl and ocrfl match in 8-bit timer mode bit 1: timer c interrupt request flag (irrtc) bit 1 irrtc description 0 clearing conditions: (initial value) when irrtc= 1, it is cleared by writing 0 1 setting conditions: when the timer c counter value overflows (from h'ff to h'00) or underflows (from h'00 to h'ff) 75 bit 0: asynchronous event counter interrupt request flag (irrec) bit 0 irrec description 0 clearing conditions: (initial value) when irrec = 1, it is cleared by writing 0 1 setting conditions: when ech overflows in 16-bit counter mode, or ech or ecl overflows in 8-bit counter mode 6. wakeup interrupt request register (iwpr) bit initial value read/write 7 iwpf7 0 r/w 6 iwpf6 0 r/w 5 iwpf5 0 r/w 4 iwpf4 0 r/w 3 iwpf3 0 r/w 0 iwpf0 0 r/w 2 iwpf2 0 r/w 1 iwpf1 0 r/w ** **** ** note: * only a write of 0 for flag clearing is possible iwpr is an 8-bit read/write register containing wakeup interrupt request flags. when one of pins wkp 7 to wkp 0 is designated for wakeup input and a rising or falling edge is input at that pin, the corresponding flag in iwpr is set to 1. a flag is not cleared automatically when the corresponding interrupt is accepted. flags must be cleared by writing 0. bits 7 to 0: wakeup interrupt request flags (iwpf7 to iwpf0) bit n iwpfn description 0 clearing conditions: (initial value) when iwpfn= 1, it is cleared by writing 0 1 setting conditions: when pin wkp 76 7. wakeup edge select register (wegr) bit initial value read/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 4 wkegs4 0 r/w 3 wkegs3 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w wegr is an 8-bit read/write register that specifies rising or falling edge sensing for pins wkp n. wegr is initialized to h'00 by a reset. bit n: wkp n edge select (wkegsn) bit n selects wkp n pin input sensing. bit n wkegsn description 0 wkp wkp 3.3.3 external interrupts there are 13 external interrupts: irq 4 to irq 0 and wkp 7 to wkp 0 . 1. interrupts wkp 7 to wkp 0 interrupts wkp 7 to wkp 0 are requested by either rising or falling edge input to pins wkp 7 to wkp 0 . when these pins are designated as pins wkp 7 to wkp 0 in port mode register 5 and a rising or falling edge is input, the corresponding bit in iwpr is set to 1, requesting an interrupt. recognition of wakeup interrupt requests can be disabled by clearing the ienwp bit to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when wkp 7 to wkp 0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector number 9 is assigned to interrupts wkp 7 to wkp 0 . all eight interrupt sources have the same vector number, so the interrupt-handling routine must discriminate the interrupt source. 77 2. interrupts irq 4 to irq 0 interrupts irq 4 to irq 0 are requested by input signals to pins irq 4 to irq 0 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg4 to ieg0 in iegr. when these pins are designated as pins irq 4 to irq 0 in port mode register 3 and 1 and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. recognition of these interrupt requests can be disabled individually by clearing bits ien4 to ien0 to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when irq 4 to irq 0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector numbers 8 to 4 are assigned to interrupts irq 4 to irq 0 . the order of priority is from irq 0 (high) to irq 4 (low). table 3.2 gives details. 3.3.4 internal interrupts there are 23 internal interrupts that can be requested by the on-chip peripheral modules. when a peripheral module requests an interrupt, the corresponding bit in irr1 or irr2 is set to 1. recognition of individual interrupt requests can be disabled by clearing the corresponding bit in ienr1 or ienr2. all these interrupts can be masked by setting the i bit to 1 in ccr. when internal interrupt handling is initiated, the i bit is set to 1 in ccr. vector numbers from 20 to 11 are assigned to these interrupts. table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. 78 3.3.5 interrupt operations interrupts are controlled by an interrupt controller. figure 3.2 shows a block diagram of the interrupt controller. figure 3.3 shows the flow up to interrupt acceptance. interrupt controller priority decision logic interrupt request ccr (cpu) i external or internal interrupts external interrupts or internal interrupt enable signals figure 3.2 block diagram of interrupt controller interrupt operation is described as follows. ? when an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. ? when the interrupt controller receives an interrupt request, it sets the interrupt request flag. ? from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (refer to table 3.2 for a list of interrupt priorities.) ? the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. 79 ? if the interrupt is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.4. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. ? the i bit of ccr is set to 1, masking further interrupts. ? the vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. notes: 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. 80 pc contents saved ccr contents saved i figure 3.3 flow up to interrupt acceptance 81 pc and ccr saved to stack sp (r7) sp 1 sp 2 sp 3 sp 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling notation: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr pc h pc l 1. 2. * pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word access, starting from an even-numbered address. ignored on return. * figure 3.4 stack state after completion of interrupt exception handling figure 3.5 shows a typical interrupt sequence. 82 vector fetch i nternal a ddress bus i nternal read s ignal i nternal write s ignal (2) i nternal data bus ( 16 bits) i nterrupt r equest signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp 2 (6) sp 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.5 interrupt sequence 83 3.3.6 interrupt response time table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. table 3.4 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 13 15 to 27 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction. 84 3.4 application notes 3.4.1 notes on stack area use when word data is accessed in the h8/3864 series, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @?p) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3.6. pc pc r1l pc sp sp sp h'fefc h'fefd h'feff r7 sp set to h'feff stack accessed beyond sp bsr instruction contents of pc are lost h notation: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer figure 3.6 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when rte is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to ccr while the odd address contents are ignored. 85 3.4.2 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. when an external interrupt pin function is switched by rewriting the port mode register that controls pins irq 4 to irq 0 , wkp 7 to wkp 0 , the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching pin functions. table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. table 3.5 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irr1 irri4 when pmr1 bit irq4 is changed from 0 to 1 while pin irq irq irq irq irq irq irq irq irq irq wkp wkp wkp wkp wkp wkp wkp wkp 86 figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 figure 3.7 port mode register setting and interrupt request flag clearing procedure 87 section 4 clock pulse generators 4.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 block diagram figure 4.1 shows a block diagram of the clock pulse generators. system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider system clock pulse generator subclock pulse generator prescaler s (13 bits) prescaler w (5 bits) osc osc 1 2 x x 1 2 osc (f ) osc w w (f ) w ? /2 osc ? /2 w ? /8 w sub ?2 to ?8192 ? /2 w ? /4 w ? /8 to ? /128 w w osc /128 osc /64 osc /32 osc /16 ? /4 w figure 4.1 block diagram of clock pulse generators 4.1.2 system clock and subclock the basic clock signals that drive the cpu and on-chip peripheral modules are ?and sub . four of the clock signals have names: ?is the system clock, sub is the subclock, osc is the oscillator clock, and w is the watch clock. the clock signals available for use by peripheral modules are ?2, ?4, ?8, ?16, ?32, ?64, ?128, ?256, ?512, ?1024, ?2048, ?4096, ?8192, w , w /2, w /4, w /8, w /16, w /32, w /64, and w /128. the clock requirements differ from one module to another. 88 4.2 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. connecting a crystal oscillator figure 4.2 shows a typical method of connecting a crystal oscillator. 1 2 c 1 c 2 osc osc r = 1 m 20% f ? r f frequency 1.0 mhz 4.0 mhz crystal oscillator ndk ndk c 1 , c 2 recommendation value 27 pf 10% 12 pf 20% products name nr-18 (ndk45) nr-18 (ndk03) figure 4.2 typical connection to crystal oscillator figure 4.3 shows the equivalent circuit of a crystal oscillator. an oscillator having the characteristics given in table 4.1 should be used. c s c 0 r s o sc 1 osc 2 l s figure 4.3 equivalent circuit of crystal oscillator table 4.1 crystal oscillator parameters frequency (mhz) 1 4.193 rs max ( ) 40 100 c 0 (pf) 3.5 pf max 16 pf 89 2. connecting a ceramic oscillator figure 4.4 shows a typical method of connecting a ceramic oscillator. 1 2 c 1 c 2 osc osc r f r = 1 m 20% f ? frequency 1.0 mhz 4.0 mhz ceramic oscillator murata murata c 1 , c 2 recommendation value 150 pf 10% 30 pf 10% products name csb 1000j csa 4.00mg figure 4.4 typical connection to ceramic oscillator 3. notes on board design when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 4.5.) the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . osc osc c 1 c 2 signal a signal b 2 1 to be avoided figure 4.5 board design of oscillator circuit 90 4. external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 4.6 shows a typical connection. 1 2 osc osc external clock input open figure 4.6 external clock input (example) frequency oscillator clock ( osc ) duty cycle 45% to 55% note: the circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. the circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. when using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 91 4.3 subclock generator 1. connecting a 32.768-khz/38.4 khz crystal oscillator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz/38.4 khz crystal oscillator, as shown in figure 4.7. follow the same precautions as noted under 3. notes on board design for the system clock in 4.2. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 frequency 32.768 khz 38.4 khz crystal oscillator ndk seiko instrument inc. products name mx73p vtc-200 figure 4.7 typical connection to 32.768-khz/38.4 khz crystal oscillator (subclock) figure 4.8 shows the equivalent circuit of the 32.768-khz/38.4 khz crystal oscillator. c s c 0 lr s x 1 x 2 c = 1.5 pf typ r = 14 k typ f = 32.768 khz/38.4khz 0 s w ? s figure 4.8 equivalent circuit of 32.768-khz/38.4 khz crystal oscillator 92 2. pin connection when not using subclock when the subclock is not used, connect pin x 1 to gnd and leave pin x 2 open, as shown in figure 4.9. x x 1 2 gnd open figure 4.9 pin connection when not using subclock 3. external clock input connect the external clock to the x1 pin and leave the x2 pin open, as shown in figure 4.10. x 1 v cc external clock input x 2 open figure 4.10 pin connection when inputting external clock frequency subclock (?) duty 45% to 55% 93 4.4 prescalers the h8/3864 series is equipped with two on-chip prescalers having different input clocks (prescaler s and prescaler w). prescaler s is a 13-bit counter using the system clock (? as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is a 5-bit counter using a 32.768-khz or 38.4 khz signal divided by 4 ( w /4) as its input clock. its prescaled outputs are used by timer a as a time base for timekeeping. 1. prescaler s (pss) prescaler s is a 13-bit counter using the system clock (? as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by timer a, timer c, timer f, timer g, sci3-1, sc3-2, the a/d converter, the lcd controller, the watchdog timer, and the 14-bit pwm. the divider ratio can be set separately for each on-chip peripheral function. in active (medium-speed) mode the clock input to prescaler s is ?sc/16, ?sc/32, ?sc/64, or ?sc/128. 2. prescaler w (psw) prescaler w is a 5-bit counter using a 32.768 khz/38.4 khz signal divided by 4 ( w /4) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x1 and x2. prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma). output from prescaler w can be used to drive timer a, in which case timer a functions as a time base for timekeeping. 94 4.5 note on oscillators oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask rom and ztat versions, referring to the examples shown in this section. oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the oscillator element manufacturer. design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 95 section 5 power-down modes 5.1 overview the h8/3864 series has nine modes of operation after a reset. these include eight power-down modes, in which power dissipation is significantly reduced. table 5.1 gives a summary of the eight operating modes. table 5.1 operating modes operating mode description active (high-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in high-speed operation active (medium-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in low-speed operation subactive mode the cpu is operable on the subclock in low-speed operation sleep (high-speed) mode the cpu halts. on-chip peripheral functions are operable on the system clock sleep (medium-speed) mode the cpu halts. on-chip peripheral functions operate at a frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock frequency subsleep mode the cpu halts. the time-base function of timer a, timer c, timer g, timer f,wdt, sci3-1, sci3-2, aec and lcd controller/driver are operable on the subclock watch mode the cpu halts. the time-base function of timer a, timer f, timer g, aec and lcd controller/driver are operable on the subclock standby mode the cpu and all on-chip peripheral functions halt module standby mode individual on-chip peripheral functions specified by software enter standby mode and halt of these nine operating modes, all but the active (high-speed) mode are power-down modes. in this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode. 96 figure 5.1 shows the transitions among these operation modes. table 5.2 indicates the internal states in each mode. program halt state sleep instruction * e sleep instruction * c sleep instruction * h sleep instruction * i sleep instruction * g sleep instruction * f program execution state sleep instruction * a program halt state sleep instruction * i power-down modes a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that interrupt handling is performed after the interrupt is accepted. details on the mode transition conditions are given in the explanations of each mode, in sections 5-2 through 5-8. notes: 1. 2. mode transition conditions (1) a b c d e f g h i j lson mson ssby dton 0 0 1 0 ? 0 0 0 1 0 0 1 ? ? ? 0 1 1 ? 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 * : don? care mode transition conditions (2) 1 interrupt sources timer a, timer f, timer g interrupt, irq 0 interrupt, wkp 7 to wkp 0 interrupts timer a, timer c, timer f, timer g, sci3-1, sci3-2 interrupt, irq 4 to irq 0 interrupts, wkp 7 to wkp 0 interrupts, aec all interrupts irq 1 or irq 0 interrupt, wkp 7 to wkp 0 interrupts 2 3 4 * 3 * 3 * 2 * 1 * 4 * 4 * 1 standby mode watch mode subactive mode active (medium-speed) mode active (high-speed) mode sleep (high-speed) mode sleep (medium-speed) mode subsleep mode sleep instruction * a sleep instruction * e sleep instruction * d sleep instruction * b sleep instruction * j * 1 sleep instruction * e sleep instruction * b tma3 ? ? 1 0 1 ? ? 1 1 1 sleep instruction * d reset state figure 5.1 mode transition diagram 97 table 5.2 internal state in each operating mode active mode sleep mode function high- speed medium- speed high- speed medium- speed watch mode subactive mode subsleep mode standby mode system clock oscillator functions functions functions functions halted halted halted halted subclock oscillator functions functions functions functions functions functions functions functions cpu instructions functions functions halted halted halted functions halted halted operations ram retained retained retained retained retained registers i/o ports retained * 1 external irq 0 functions functions functions functions functions functions functions functions interrupts irq 1 retained * 6 irq 2 retained * 6 irq 3 irq 4 wkp 0 functions functions functions functions functions functions functions functions wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 peripheral timer a functions functions functions functions functions * 5 functions * 5 functions * 5 retained functions asynchronous counter functions * 8 functions functions functions * 8 timer c retained functions/ retained * 2 functions/ retained * 2 retained wdt functions/ retained * 7 retained timer g, timer f functions/ retained * 9 functions/ retained * 9 functions/ retained * 9 sci3-1 reset functions/ retained * 3 functions/ reset sci3-2 pwm retained retained retained retained a/d converter retained retained retained retained lcd functions/ retained * 4 functions/ retained * 4 functions/ retained * 4 retained notes: 1. register contents are retained, but output is high-impedance state. 2. functions if an external clock or the w /4 internal clock is selected; otherwise halted and retained. 3. functions if w /2 is selected as the internal clock; otherwise halted and retained. 4. functions if w , w /2 or w /4 is selected as the operating clock; otherwise halted and retained. 5. functions if the timekeeping time-base function is selected. 6. external interrupt requests are ignored. interrupt request register contents are not altered. 7. functions if w /32 is selected as the internal clock; otherwise halted and retained. 8. incrementing is possible, but interrupt generation is not. 9. functions if an external clock or the w /4 internal clock is selected; otherwise halted and retained. 98 5.1.1 system control registers the operation mode is selected using the system control registers described in table 5.3. table 5.3 system control registers name abbreviation r/w initial value address system control register 1 syscr1 r/w h'07 h'fff0 system control register 2 syscr2 r/w h'f0 h'fff1 1. system control register 1 (syscr1) b it i nitial value r ead/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 1 1 ma1 1 r/w syscr1 is an 8-bit read/write register for control of the power-down modes. upon reset, syscr1 is initialized to h'07. bit 7: software standby (ssby) this bit designates transition to standby mode or watch mode. bit 7 ssby description 0 ? ? ? ? 99 bits 6 to 4: standby timer select 2 to 0 (sts2 to sts0) these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. the designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 wait time = 8,192 states (initial value) 0 0 1 wait time = 16,384 states 0 1 0 wait time = 32,768 states 0 1 1 wait time = 65,536 states 1 0 0 wait time = 131,072 states 1 0 1 wait time = 2 states (external clock mode) 1 1 0 wait time = 8 states 1 1 1 wait time = 16 states note: in the case that external clock is input, set up the standby timer select selection to external clock mode before mode transition. also, do not set up to external clock mode, in the case that it does not use external clock. bit 3: low speed on flag (lson) this bit chooses the system clock (? or subclock ( sub ) as the cpu operating clock when watch mode is cleared. the resulting operation mode depends on the combination of other control bits and interrupt input. bit 3 lson description 0 the cpu operates on the system clock ( ) (initial value) 1 the cpu operates on the subclock ( sub) bits 2: reserved bits bit 2 is reserved: it is always read as 1 and cannot be modified. 100 bits 1 and 0: active (medium-speed) mode clock select (ma1, ma0) bits 1 and 0 choose osc /128, osc /64, osc /32, or osc /16 as the operating clock in active (medium- speed) mode and sleep (medium-speed) mode. ma1 and ma0 should be written in active (high- speed) mode or subactive mode. bit 1 ma1 bit 0 ma0 description 00 osc /16 01 osc /32 10 osc /64 11 osc /128 (initial value) 2. system control register 2 (syscr2) b it i nitial value r ead/write 7 1 6 1 5 1 4 nesel 1 r/w 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w syscr2 is an 8-bit read/write register for power-down mode control. bits 7 to 5: reserved bits these bits are reserved; they are always read as 1, and cannot be modified. bit 4: noise elimination sampling frequency select (nesel) this bit selects the frequency at which the watch clock signal ( w ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( osc ) generated by the system clock pulse generator. when osc = 2 to 6 mhz, clear nesel to 0. bit 4 nesel description 0 sampling rate is osc /16 1 sampling rate is osc /4 (initial value) 101 bit 3: direct transfer on flag (dton) this bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a sleep instruction is executed. the mode to which the transition is made after the sleep instruction is executed depends on a combination of this and other control bits. bit 3 dton description 0 ? ? ? ? ? bit 2: medium speed on flag (mson) after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. bit 2 mson description 0 operation in active (high-speed) mode (initial value) 1 operation in active (medium-speed) mode 102 bits 1 and 0: subactive mode clock select (sa1 and sa0) these bits select the cpu clock rate ( w /2, w /4, or w /8) in subactive mode. sa1 and sa0 cannot be modified in subactive mode. bit 1 sa1 bit 0 sa0 description 00 w /8 (initial value) 01 w /4 1 * w /2 * : don t care 103 5.2 sleep mode 5.2.1 transition to sleep mode 1. transition to sleep (high-speed) mode the system goes from active mode to sleep (high-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson and dton bits in syscr2 are cleared to 0. in sleep mode cpu operation is halted but the on-chip peripheral functions. cpu register contents are retained. 2. transition to sleep (medium-speed) mode the system goes from active mode to sleep (medium-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is cleared to 0. in sleep (medium-speed) mode, as in sleep (high-speed) mode, cpu operation is halted but the on-chip peripheral functions are operational. the clock frequency in sleep (medium-speed) mode is determined by the ma1 and ma0 bits in syscr1. cpu register contents are retained. furthermore, it sometimes acts with half state early timing at the time of transition to sleep (medium-speed) mode. 5.2.2 clearing sleep mode sleep mode is cleared by any interrupt (timer a, timer c, timer f, timer g, asynchronous counter, irq 4 to irq 0 , wkp 7 to wkp 0 , sci3-1, sci3-2, a/d converter, or), or by input at the res pin. ? clearing by interrupt when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. a transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. interrupt signal and system clock are mutually asynchronous. synchronization error time in a maximum is 2/?(s). ? clearing by res input when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 104 5.2.3 clock frequency in sleep (medium-speed) mode operation in sleep (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1. 5.3 standby mode 5.3.1 transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and bit tma3 in tma is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of cpu registers, on-chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be further retained down to a minimum ram data retention voltage. the i/o ports go to the high-impedance state. 5.3.2 clearing standby mode standby mode is cleared by an interrupt (irq 1 or irq 0 ), wkp 7 to wkp 0 or by input at the res pin. ? clearing by interrupt when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium-speed) mode if mson = 1. standby mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input when the res pin goes low, the system clock pulse generator starts. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. 105 5.3.3 oscillator settling time after standby mode is cleared bits sts2 to sts0 in syscr1 should be set as follows. ? when a crystal oscillator is used the table below gives settings for various operating frequencies. set bits sts2 to sts0 for a waiting time at least as long as the oscillation settling time. table 5.4 clock frequency and settling time (times are in ms) sts2 sts1 sts0 waiting time 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 4.1 8.2 16.4 0 0 1 16,384 states 8.2 16.4 32.8 0 1 0 32,768 states 16.4 32.8 65.5 0 1 1 65,536 states 32.8 65.5 131.1 1 0 0 131,072 states 65.5 131.1 262.1 1 0 1 2 states (use prohibited) 0.001 0.002 0.004 1 1 0 8 states 0.004 0.008 0.016 1 1 1 16 states 0.008 0.016 0.032 ? when an external clock is used sts2 = 1, sts1 = 0, and sts0 = 1 should be set. other values possible use, but cpu sometimes will start operation before waiting time completion. 106 5.3.4 standby mode transition and pin states when a sleep instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, and bit tma3 is cleared to 0 in tma, a transition is made to standby mode. at the same time, pins go to the high- impedance state (except pins for which the pull-up mos is designated as on). figure 5.2 shows the timing in this case. sleep instruction fetch internal data bus fetch of next instruction port output pins high-impedance active (high-speed) mode or active (medium-speed) mode standby mode sleep instruction execution internal processing figure 5.2 standby mode transition and pin states 107 5.4 watch mode 5.4.1 transition to watch mode the system goes from active or subactive mode to watch mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1. in watch mode, operation of on-chip peripheral modules is halted except for timer a, timer f, timer g, aec and the lcd controller/driver (for which operation or halting can be set) is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules, are retained. i/o ports keep the same states as before the transition. 5.4.2 clearing watch mode watch mode is cleared by an interrupt (timer a, timer f, timer g, irq 0 , or wkp 7 to wkp 0 ) or by input at the res pin. ? clearing by interrupt when watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of lson in syscr1 and mson in syscr2. if both lson and mson are cleared to 0, transition is to active (high-speed) mode; if lson = 0 and mson = 1, transition is to active (medium-speed) mode; if lson = 1, transition is to subactive mode. when the transition is to active mode, after the time set in syscr1 bits sts2 to sts0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. watch mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input clearing by res pin is the same as for standby mode; see 2. clearing by res pin in 5.3.2, clearing standby mode. 5.4.3 oscillator settling time after watch mode is cleared the waiting time is the same as for standby mode; see 5.3.3, oscillator settling time after standby mode is cleared. 108 5.5 subsleep mode 5.5.1 transition to subsleep mode the system goes from subactive mode to subsleep mode when a sleep instruction is executed while the ssby bit in syscr1 is cleared to 0, lson bit in syscr1 is set to 1, and tma3 bit in tma is set to 1. in subsleep mode, operation of on-chip peripheral modules other than the a/d converter wdt and pwm is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. 5.5.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a, timer c, timer f, timer g, asynchronous counter, sci3-2, sci3-1, irq 4 to irq 0 , wkp 7 to wkp 0 ) or by a low input at the res pin. ? clearing by interrupt when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. interrupt signal and system clock are mutually asynchronous. synchronization error time in a maximum is 2/?(s). ? clearing by res input clearing by res pin is the same as for standby mode; see 2. clearing by res pin in 5.3.2, clearing standby mode. 109 5.6 subactive mode 5.6.1 transition to subactive mode subactive mode is entered from watch mode if a timer a, timer f, timer g, irq 0 , or wkp 7 to wkp 0 interrupt is requested while the lson bit in syscr1 is set to 1. from subsleep mode, subactive mode is entered if a timer a, timer c, timer f, timer g, asynchronous counter, sci3-1, sci3-2, irq 4 to irq 0 , or wkp 7 to wkp 0 interrupt is requested. a transition to subactive mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 clearing subactive mode subactive mode is cleared by a sleep instruction or by a low input at the res pin. ? clearing by sleep instruction if a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and tma3 bit in tma is set to 1, subactive mode is cleared and watch mode is entered. if a sleep instruction is executed while ssby = 0 and lson = 1 in syscr1 and tma3 = 1 in tma, subsleep mode is entered. direct transfer to active mode is also possible; see 5.8, direct transfer, below. ? clearing by res pin clearing by res pin is the same as for standby mode; see 2. clearing by res pin in 5.3.2, clearing standby mode. 5.6.3 operating frequency in subactive mode the operating frequency in subactive mode is set in bits sa1 and sa0 in syscr2. the choices are w /2, w /4, and w /8. 110 5.7 active (medium-speed) mode 5.7.1 transition to active (medium-speed) mode if the res pin is driven low, active (medium-speed) mode is entered. if the lson bit in syscr2 is set to 1 while the lson bit in syscr1 is cleared to 0, a transition to active (medium-speed) mode results from irq 0 , irq 1 or wkp 7 to wkp 0 interrupts in standby mode, timer a, timer f, timer g, irq 0 or wkp 7 to wkp 0 interrupts in watch mode, or any interrupt in sleep mode. a transition to active (medium-speed) mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. furthermore, it sometimes acts with half state early timing at the time of transition to active (medium-speed) mode. 5.7.2 clearing active (medium-speed) mode active (medium-speed) mode is cleared by a sleep instruction. ? clearing by sleep instruction a transition to standby mode takes place if the sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and the tma3 bit in tma is cleared to 0. the system goes to watch mode if the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1 when a sleep instruction is executed. when both ssby and lson are cleared to 0 in syscr1 and a sleep instruction is executed, sleep mode is entered. direct transfer to active (high-speed) mode or to subactive mode is also possible. see 5.8, direct transfer, below for details. ? clearing by res pin when the res pin is driven low, a transition is made to the reset state and active (medium-speed) mode is cleared. 5.7.3 operating frequency in active (medium-speed) mode operation in active (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1. 111 5.8 direct transfer 5.8.1 overview of direct transfer the cpu can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. a direct transfer is a transition among these three modes without the stopping of program execution. a direct transfer can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. after the mode transition, direct transfer interrupt exception handling starts. if the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead to sleep mode or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. ? direct transfer from active (high-speed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. ? direct transfer from active (medium-speed) mode to active (high-speed) mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. ? direct transfer from active (high-speed) mode to subactive mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 112 ? direct transfer from active (medium-speed) mode to subactive mode when a sleep instruction is executed in active (medium-speed) while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 5.8.2 direct transition times 1. time for direct transition from active (high-speed) mode to active (medium-speed) mode a direct transition from active (high-speed) mode to active (medium-speed) mode is performed by executing a sleep instruction in active (high-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bits mson and dton are both set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (1) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (1) example: direct transition time = (2 + 1) 2tosc + 14 16tosc = 230tosc (when ?8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock (? cycle time 113 2. time for direct transition from active (medium-speed) mode to active (high-speed) mode a direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a sleep instruction in active (medium-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bit mson is cleared to 0 and bit dton is set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (2) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (2) example: direct transition time = (2 + 1) 16tosc + 14 2tosc = 76tosc (when ?8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock (? cycle time 3. time for direct transition from subactive mode to active (high-speed) mode a direct transition from subactive mode to active (high-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bit mson is cleared to 0 and bit dton is set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (3) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (3) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 2tosc = 24tw + 16412tosc (when ?/8 is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock (? cycle time tsubcyc: subclock (?ub) cycle time 114 4. time for direct transition from subactive mode to active (medium-speed) mode a direct transition from subactive mode to active (medium-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bits mson and dton are both set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (4) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (4) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 16tosc = 24tw + 131296tosc (when ?/8 or ? is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock (? cycle time tsubcyc: subclock (?ub) cycle time 115 5.9 module standby mode 5.9.1 setting module standby mode module standby mode is set for individual peripheral functions. all the on-chip peripheral modules can be placed in module standby mode. when a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. this state is identical to standby mode. module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) 5.9.2 clearing module standby mode module standby mode is cleared for a particular module by setting the corresponding bit to 1 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) following a reset, clock stop register 1 (ckstpr1) and clock stop register 2 (ckstpr2) are both initialized to h'ff. table 5.5 register name bit name operation ckstpr1 tackstp 1 timer a module standby mode is cleared 0 timer a is set to module standby mode tcckstp 1 timer c module standby mode is cleared 0 timer c is set to module standby mode tfckstp 1 timer f module standby mode is cleared 0 timer f is set to module standby mode tgckstp 1 timer g module standby mode is cleared 0 timer g is set to module standby mode adckstp 1 a/d converter module standby mode is cleared 0 a/d converter is set to module standby mode s32ckstp 1 sci3-2 module standby mode is cleared 0 sci3-2 is set to module standby mode s31ckstp 1 sci3-1 module standby mode is cleared 0 sci3-1 is set to module standby mode 116 table 5.5 (cont) register name bit name operation ckstpr2 ldckstp 1 lcd module standby mode is cleared 0 lcd is set to module standby mode pwckstp 1 pwm module standby mode is cleared 0 pwm is set to module standby mode wdckstp 1 watchdog timer module standby mode is cleared 0 watchdog timer is set to module standby mode aeckstp 1 asynchronous event counter module standby mode is cleared 0 asynchronous event counter is set to module standby mode note: for details of module operation, see the sections on the individual modules. 117 section 6 rom 6.1 overview the h8/3862 and h8/3822 have 16 kbytes of on-chip mask rom, the h8/3863 and h8/3823 have 24 kbytes, the h8/3864 and h8/3824 have 32 kbytes, the h8/3865 and h8/3825 have 40 kbytes, the h8/3866 and h8/3826 have 48 kbytes, and the h8/3867 and h8/3827 have 60 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. the h8/3867 and h8/3827 have a ztat version with 60-kbyte prom. 6.1.1 block diagram figure 6.1 shows a block diagram of the on-chip rom. h'7ffe h'7fff internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'7ffe h'0002 h'0000 h'0000 h'0002 h'0001 h'0003 on-chip rom figure 6.1 rom block diagram (h8/3864 and h8/3824) 118 6.2 h8/3867 and h8/3827 prom mode 6.2.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the standard hn27c101 eprom. however, page programming is not supported. table 6.1 shows how to set the chip to prom mode. table 6.1 setting to prom mode pin name setting test high level pb 4 /an 4 low level pb 5 /an 5 pb 6 /an 6 high level 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 32 pins, as listed in table 6.2. figure 6.2 shows the pin-to-pin wiring of the socket adapter. figure 6.3 shows a memory map. table 6.2 socket adapter package socket adapters (manufacturer) 80-pin (fp-80b) me3867esfs1h (minato) h7386bq080d3201 (data-i/o) 80-pin (fp-80a) me3867eshs1h (minato) h7386aq080d3201 (data-i/o) 80-pin (tfp-80c) me3867esns1h (minato) h7386ct080d3201 (data-i/o) 119 fp-80a , tfp-80c fp-80b pin 9 45 46 47 48 49 50 51 52 68 67 66 65 64 63 62 61 53 72 55 56 57 58 59 14 15 60 54 13 32, 26 73 8 3 80 11 12 16 5, 27 2 78 79 11 47 48 49 50 51 52 53 54 70 69 68 67 66 65 64 63 55 74 57 58 59 60 61 16 17 62 56 15 34, 28 75 10 5 2 13 14 18 7, 29 4 80 1 hn27c101 (32-pin) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 res p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 0 p4 3 p7 2 p7 3 p7 4 p7 5 p7 6 p1 4 p1 5 p7 7 p7 1 p1 3 v cc , cv cc av cc test x 1 pb 6 p1 1 p1 2 p1 6 v ss av ss pb 4 pb 5 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 ce oe pgm v cc v ss note: pins not indicated in the figure should be left open. h8/3867 and h8/3827 eprom socket figure 6.2 socket adapter pin correspondence (with hn27c101) 120 address in mcu mode address in prom mode h'0000 h'0000 h'1ffff h'edff h'edff on-chip prom uninstalled area * the output data is not guaranteed if this address area is read in prom mode. there- fore, when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if programming is inadvertently performed from h'ee00 onward, it may not be possible to continue prom programming and verification. when programming, h'ff should be set as the data in this address area (h'ee00 to h'1ffff). note: * figure 6.3 h8/3867 and h8/3827 memory map in prom mode 121 6.3 h8/3867 and h8/3827 programming the write, verify, and other modes are selected as shown in table 6.3 in h8/3867 and h8/3827 prom mode. table 6.3 mode selection in prom mode (h8/3867, h8/3827) pins mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write l h l v pp v cc data input address input verify l l h v pp v cc data output address input programming l l l v pp v cc high impedance address input disabled l h h hl l hhh notation l: low level h: high level v pp :v pp level v cc :v cc level the specifications for writing and reading are identical to those for the standard hn27c101 eprom. however, page programming is not supported, and so page programming mode must not be set. a prom programmer that only supports page programming mode cannot be used. when selecting a prom programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. also, be sure to specify addresses from h'0000 to h'edff. 6.3.1 writing and verifying an efficient, high-speed, high-reliability method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. the basic flow of this high-speed, high-reliability programming method is shown in figure 6.4. 122 start set write/verify mode v = 6.0 v 0.25 v, v = 12.5 v 0.3 v cc pp address = 0 n = 0 n + 1 n pw verify write time t = 3n ms opw last address? set read mode v = 5.0 v 0.25 v, v = v cc pp cc read all addresses? end error n 25 < address + 1 address no yes no go go yes no no go go write time t = 0.2 ms 5% figure 6.4 high-speed, high-reliability programming flow chart 123 table 6.4 and table 6.5 give the electrical characteristics in programming mode. table 6.4 dc characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25 c ? c) item symbol min typ max unit test condition input high- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v ih 2.4 v cc + 0.3 v input low- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v il ?.3 0.8 v output high- level voltage eo 7 to eo 0 v oh 2.4 v i oh = ?00 ? output low- level voltage eo 7 to eo 0 v ol 0.45 v i ol = 0.8 ma input leakage current eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm |il i | 2 ? v in = 5.25 v/ 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma 124 table 6.5 ac characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25 c ? c) item symbol min typ max unit test condition address setup time t as 2 s figure 6.5 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 5.25 ms ce setup time t ces 2 s v cc setup time t vcs 2 s data output delay time t oe 0 200 ns notes: 1. input pulse level: 0.45 v to 2.2 v input rise time/fall time 20 ns timing reference levels input: 0.8 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in figure 6.4, high-speed, high-reliability programming flow chart. 125 figure 6.5 shows a prom write/verify timing diagram. write input data output data verify address data v pp v pp t as t ah t ds t dh t df t oe t oes t pw t opw * t vps t vcs t ces v cc v cc ce pgm oe v cc +1 v cc note: * t opw is defined by the value shown in figure 6.4, high-speed, high-reliability programming flowchart. figure 6.5 prom write/verify timing 126 6.3.2 programming precautions ? ? ? ? ? 127 6.4 reliability of programmed data a highly effective way to improve data retention characteristics is to bake the programmed chips at 150 c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 6.6 shows the recommended screening procedure. program chip and verify programmed data bake chip for 24 to 48 hours at 125 figure 6.6 recommended screening procedure if a series of programming errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. 128 129 section 7 ram 7.1 overview the h8/3862, h8/3863, h8/3822, and h8/3823 have 1 kbyte of high-speed static ram on-chip, and the h8/3864, h8/3865, h8/3866, h8/3867, h8/3824, h8/3825, h8/3826, and h8/3827 have 2 kbytes. the ram is connected to the cpu by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 block diagram figure 7.1 shows a block diagram of the on-chip ram. h'ff7e h'ff7f internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'ff7e h'f782 h'f780 h'f780 h'f782 h'f781 h'f783 on-chip ram figure 7.1 ram block diagram (h8/3864 and h8/3824) 130 131 section 8 i/o ports 8.1 overview the h8/3864 series is provided with six 8-bit i/o ports, one 4-bit i/o port, one 3-bit i/o port, one 8-bit input-only port, and one 1-bit input-only port. table 8.1 indicates the functions of each port. each port has of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be assigned to individual bits. see 2.9.2, notes on bit manipulation, for information on executing bit-manipulation instructions to write data in pcr or pdr. ports 5, 6, 7, 8, and a are also used as liquid crystal display segment and common pins, selectable in 8-bit units. block diagrams of each port are given in appendix c, i/o port block diagrams. table 8.1 port functions port description pins other functions function switching registers port 1 ? 8-bit i/o port ? mos input pull-up option p1 7 to p1 5 / irq 3 to irq 1 / tmif, tmic external interrupts 3 to 1 timer event interrupts tmif, tmic pmr1 tcrf, tmc p1 4 / irq 4 / adtrg external interrupt 4 and a/d converter external trigger pmr1, amr p1 3 /tmig timer g input capture input pmr1 p1 2 , p1 1 / tmofh, tmofl timer f output compare output pmr1 p1 0 /tmow timer a clock output pmr1 port 3 ? 8-bit i/o port ? mos input pull-up option ? large-current port p3 7 /aevl p3 6 /aevh p3 5 /txd 31 p3 4 /rxd 31 p3 3 /sck 31 sci3-1 data output (txd 31 ), data input (rxd 31 ), clock input/output (sck 31 ), and asynchronous counter event inputs aevl, aevh pmr3 scr31 smr31 p3 2 / reso p3 1 /ud p3 0 /pwm reset output, timer c count- up/down select input, and 14- bit pwm output pmr3 132 table 8.1 port functions (cont) port description pins other functions function switching registers port 4 ? 1-bit input port p4 3 / irq 0 external interrupt 0 pmr3 ? 3-bit i/o port p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 sci3-2 data output (txd 32 ), data input (rxd 32 ), clock input/output (sck 32 ) scr32 smr32 port 5 ? 8-bit i/o port ? mos input pull-up option p5 7 to p5 0 / wkp 7 to wkp 0 / seg 8 to seg 1 wakeup input ( wkp 7 to wkp 0 ), segment output (seg 8 to seg 1 ) pmr5 lpcr port 6 ? 8-bit i/o port ? mos input pull-up option p6 7 to p6 0 / seg 16 to seg 9 segment output (seg 16 to seg 9 ) lpcr port 7 ? 8-bit i/o port p7 7 to p7 0 / seg 24 to seg 17 segment output (seg 24 to seg 17 ) lpcr port 8 ? 8-bit i/o port p8 7 /seg 32 /cl 1 p8 6 /seg 31 /cl 2 p8 5 /seg 30 /do p8 4 /seg 29 /m p8 3 to p8 0 / seg 28 to seg 25 segment output (seg 32 to seg 25 ) segment external expansion latch clock (cl 1 ), shift clock (cl 2 ), display data (do), alternation signal (m) lpcr port a 4-bit i/o port pa 3 to pa 0 / com 4 to com 1 common output (com 4 to com 1 ) lpcr port b 8-bit input port pb 7 to pb 0 / an 7 to an 0 a/d converter analog input amr 133 8.2 port 1 8.2.1 overview port 1 is a 8-bit i/o port. figure 8.1 shows its pin configuration. p1 /irq /tmif p1 /irq p1 /irq /tmic p1 / irq / adtrg p1 /tmig 7 6 5 4 3 3 2 1 4 port 1 p1 /tmofh p1 /tmofl p1 /tmow 2 1 0 figure 8.1 port 1 pin configuration 8.2.2 register configuration and description table 8.2 shows the port 1 register configuration. table 8.2 port 1 registers name abbrev. r/w initial value address port data register 1 pdr1 r/w h'00 h'ffd4 port control register 1 pcr1 w h'00 h'ffe4 port pull-up control register 1 pucr1 r/w h'00 h'ffe0 port mode register 1 pmr1 r/w h'00 h'ffc8 134 1. port data register 1 (pdr1) b it i nitial value r ead/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 76543210 pdr1 is an 8-bit register that stores data for port 1 pins p1 7 to p1 0 . if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are read, regardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. upon reset, pdr1 is initialized to h'00. 2. port control register 1 (pcr1) b it i nitial value r ead/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w 76543210 pcr1 is an 8-bit register for controlling whether each of the port 1 pins p1 7 to p1 0 functions as an input pin or output pin. setting a pcr1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr1 and in pdr1 are valid only when the corresponding pin is designated in pmr1 as a general i/o pin. upon reset, pcr1 is initialized to h'00. pcr1 is a write-only register, which is always read as all 1s. 135 3. port pull-up control register 1 (pucr1) bit initial value read/write 7 pucr1 0 r/w 6 pucr1 0 r/w 5 pucr1 0 r/w 4 pucr1 0 r/w 3 pucr1 0 r/w 0 pucr1 0 r/w 2 pucr1 0 r/w 1 pucr1 0 r/w 7 65 4 32 10 pucr1 controls whether the mos pull-up of each of the port 1 pins p1 7 to p1 0 is on or off. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr1 is initialized to h'00. 4. port mode register 1 (pmr1) bit initial value read/write 7 irq3 0 r/w 6 irq2 0 r/w 5 irq1 0 r/w 4 irq4 0 r/w 3 tmig 0 r/w 0 tmow 0 r/w 2 tmofh 0 r/w 1 tmofl 0 r/w pmr1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. upon reset, pmr1 is initialized to h'00. bit 7: p1 7 / irq 3 /tmif pin function switch (irq3) this bit selects whether pin p1 7 / irq 3 /tmif is used as p1 7 or as irq 3 /tmif. bit 7 irq3 description 0 functions as p1 7 i/o pin (initial value) 1 functions as irq 3 /tmif input pin note: rising or falling edge sensing can be designated for irq 3 , tmif. for details on tmif settings, see 3. timer control register f (tcrf) in 9.4.2. 136 bit 6: p1 6 / irq 2 pin function switch (irq2) this bit selects whether pin p1 6 / irq 2 is used as p1 6 or as irq 2 . bit 6 irq2 description 0 functions as p1 6 i/o pin (initial value) 1 functions as irq 2 input pin note: rising or falling edge sensing can be designated for irq 2 . bit 5: p1 5 / irq 1 /tmic pin function switch (irq1) this bit selects whether pin p1 5 / irq 1 /tmic is used as p1 5 or as irq 1 /tmic. bit 5 irq1 description 0 functions as p1 5 i/o pin (initial value) 1 functions as irq 1 /tmic input pin note: rising or falling edge sensing can be designated for irq 1 /tmic. for details of tmic pin setting, see 1. timer mode register c (tmc) in 9.3.2. bit 4: p1 4 / irq 4 / adtrg pin function switch (irq4) this bit selects whether pin p1 4 / irq 4 / adtrg is used as p1 4 or as irq 4 / adtrg . bit 4 irq4 description 0 functions as p1 4 i/o pin (initial value) 1 functions as irq 4 / adtrg input pin note: for details of adtrg pin setting, see 12.3.2, start of a/d conversion by external trigger. bit 3: p1 3 /tmig pin function switch (tmig) this bit selects whether pin p1 3 /tmig is used as p1 3 or as tmig. bit 3 tmig description 0 functions as p1 3 i/o pin (initial value) 1 functions as tmig input pin 137 bit 2: p1 2 /tmofh pin function switch (tmofh) this bit selects whether pin p1 2 /tmofh is used as p1 2 or as tmofh. bit 2 tmofh description 0 functions as p1 2 i/o pin (initial value) 1 functions as tmofh output pin bit 1: p1 1 /tmofl pin function switch (tmofl) this bit selects whether pin p1 1 /tmofl is used as p1 1 or as tmofl. bit 1 tmofl description 0 functions as p1 1 i/o pin (initial value) 1 functions as tmofl output pin bit 0: p1 0 /tmow pin function switch (tmow) this bit selects whether pin p1 0 /tmow is used as p1 0 or as tmow. bit 0 tmow description 0 functions as p1 0 i/o pin (initial value) 1 functions as tmow output pin 138 8.2.3 pin functions table 8.3 shows the port 1 pin functions. table 8.3 port 1 pin functions pin pin functions and selection method p1 7 / irq 3 /tmif the pin function depends on bit irq3 in pmr1, bits cksl2 to cksl0 in tcrf, and bit pcr1 7 in pcr1. irq 3 01 pcr1 7 01 * cksl2 to cksl0 * not 0 ** 0 ** pin function p1 7 input pin p1 7 output pin irq 3 input pin irq 3 /tmif input pin note: when this pin is used as the tmif input pin, clear bit ien3 to 0 in ienr1 to disable the irq 3 interrupt. p1 6 / irq 2 the pin function depends on bits irq2 in pmr1 and bit pcr1 6 in pcr1. irq2 0 1 pcr1 6 01 * pin function p1 6 input pin p1 6 output pin irq 2 input pin p1 5 / irq 1 tmic the pin function depends on bit irq1 in pmr1, bits tmc2 to tmc0 in tmc, and bit pcr1 5 in pcr1. irq1 0 1 pcr1 5 01 * tmc2 to tmc0 * not 111 111 pin function p1 5 input pin p1 5 output pin irq 1 input pin irq 1 /tmic input pin note: when this pin is used as the tmic input pin, clear bit ien1 to 0 in ienr1 to disable the irq 1 interrupt. p1 4 / irq 4 adtrg the pin function depends on bit irq4 in pmr1, bit trge in amr, and bit pcr1 4 in pcr1. irq4 0 1 pcr1 4 01 * trge * 01 pin function p1 4 input pin p1 4 output pin irq 4 input pin irq 4 / adtrg input pin note: when this pin is used as the adtrg input pin, clear bit ien4 to 0 in ienr1 to disable the irq 4 interrupt. 139 table 8.3 port 1 pin functions (cont) pin pin functions and selection method p1 3 /tmig the pin function depends on bit tmig in pmr1 and bit pcr1 3 in pcr1. tmig 0 1 pcr1 3 01 * pin function p1 3 input pin p1 3 output pin tmig input pin p1 2 /tmofh the pin function depends on bit tmofh in pmr1 and bit pcr1 2 in pcr1. tmofh 0 1 pcr1 2 01 * pin function p1 2 input pin p1 2 output pin tmofh output pin p1 1 /tmofl the pin function depends on bit tmofl in pmr1 and bit pcr1 1 in pcr1. tmofl 0 1 pcr1 1 01 * pin function p1 1 input pin p1 1 output pin tmofl output pin p1 0 /tmow the pin function depends on bit tmow in pmr1 and bit pcr1 0 in pcr1. tmow 0 1 pcr1 0 01 * pin function p1 0 input pin p1 0 output pin tmow output pin * : don? care 140 8.2.4 pin states table 8.4 shows the port 1 pin states in each operating mode. table 8.4 port 1 pin states pins reset sleep subsleep standby watch subactive active p1 7 / irq 3 /tmif p1 6 / irq 2 p1 5 / irq 1 /tmic p1 4 / irq 4 / adtrg p1 3 /tmig p1 2 /tmofh p1 1 /tmofl p1 0 /tmow high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.2.5 mos input pull-up port 1 has a built-in mos input pull-up function that can be controlled by software. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset. pcr1 n 00 1 pucr1 n 01 * mos input pull-up off on off (n = 7 to 0) * : don? care 141 8.3 port 3 8.3.1 overview port 3 is a 8-bit i/o port, configured as shown in figure 8.2. p3 /aevl p3 /aevh p3 /txd 7 6 5 port 3 31 p3 /rxd p3 /sck p3 /reso 4 3 2 31 31 p3 /ud p3 /pwm 1 0 figure 8.2 port 3 pin configuration 8.3.2 register configuration and description table 8.5 shows the port 3 register configuration. table 8.5 port 3 registers name abbrev. r/w initial value address port data register 3 pdr3 r/w h'00 h'ffd6 port control register 3 pcr3 w h'00 h'ffe6 port pull-up control register 3 pucr3 r/w h'00 h'ffe1 port mode register 3 pmr3 r/w h'04 h'ffca 142 1. port data register 3 (pdr3) b it i nitial value r ead/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 r/w 2 p3 0 r/w 1 p3 0 r/w 210 54 76 3 pdr3 is an 8-bit register that stores data for port 3 pins p3 7 to p3 0 . if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, regardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. upon reset, pdr3 is initialized to h'00. 2. port control register 3 (pcr3) b it i nitial value r ead/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w 21 0 54 3 76 pcr3 is an 8-bit register for controlling whether each of the port 3 pins p3 7 to p3 0 functions as an input pin or output pin. setting a pcr3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid only when the corresponding pin is designated in pmr3 as a general i/o pin. upon reset, pcr3 is initialized to h'00. pcr3 is a write-only register, which is always read as all 1s. 3. port pull-up control register 3 (pucr3) b it i nitial value r ead/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 2 10 5 43 76 pucr3 controls whether the mos pull-up of each of the port 3 pins p3 7 to p3 0 is on or off. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr3 is initialized to h'00. 143 4. port mode register 3 (pmr3) bit initial value read/write 7 aevl 0 r/w 6 aevh 0 r/w 5 wdcks 0 r/w 4 ncs 0 r/w 3 irq0 0 r/w 0 pwm 0 r/w 2 reso 1 r/w 1 ud 0 r/w pmr3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. upon reset, pmr3 is initialized to h'04. bit 7: p3 7 /aevl pin function switch (aevl) this bit selects whether pin p3 7 /aevl is used as p3 7 or as aevl. bit 7 aevl description 0 functions as p3 7 i/o pin (initial value) 1 functions as aevl input pin bit 6: p3 6 /aevh pin function switch (aevh) this bit selects whether pin p3 6 /aevh is used as p3 6 or as aevh. bit 6 aevh description 0 functions as p3 6 i/o pin (initial value) 1 functions as aevh input pin bit 5: watchdog timer source clock select (wdcks) this bit selects the watchdog timer source clock. bit 5 wdcks description 0 /8192 selected (initial value) 1 w/32 selected 144 bit 4: tmig noise canceler select (ncs) this bit controls the noise canceler for the input capture input signal (tmig). bit 4 ncs description 0 noise cancellation function not used (initial value) 1 noise cancellation function used bit 3: p4 3 / irq 0 pin function switch (irq0) this bit selects whether pin p4 3 / irq 0 is used as p4 3 or as irq 0 . bit 3 irq0 description 0 functions as p4 3 input pin (initial value) 1 functions as irq bit 2: p3 2 / reso pin function switch (reso) this bit selects whether pin p3 2 / reso is used as p3 2 or as reso . bit 2 reso description 0 functions as p3 2 i/o pin 1 functions as reso bit 1: p3 1 /ud pin function switch (si1) this bit selects whether pin p3 1 /ud is used as p3 1 or as ud. bit 1 ud description 0 functions as p3 1 i/o pin (initial value) 1 functions as ud input pin 145 bit 0: p3 0 /pwm pin function switch (pwm) this bit selects whether pin p3 0 /pwm is used as p3 0 or as pwm. bit 0 pwm description 0 functions as p3 0 i/o pin (initial value) 1 functions as pwm output pin 8.3.3 pin functions table 8.9 shows the port 3 pin functions. table 8.9 port 3 pin functions pin pin functions and selection method p3 7 /aevl the pin function depends on bit so1 in pmr3 and bit pcr3 2 in pcr3. aevl 0 1 pcr3 7 01 * pin function p3 7 input pin p3 7 output pin aevl input pin p3 6 /aevh the pin function depends on bit aevh in pmr3 and bit pcr36 in pcr3. aevh 0 1 pcr3 6 01 * pin function p3 6 input pin p3 6 output pin aevh input pin p3 5 /txd 31 the pin function depends on bit te in scr3-1, bit spc31 in spcr, and bit pcr3 5 in pcr3. spc31 0 1 te 0 1 pcr3 5 01 * pin function p3 5 input pin p3 5 output pin txd 31 output pin * : don t care 146 table 8.9 port 3 pin functions (cont) pin pin functions and selection method p3 4 /rxd 31 the pin function depends on bit re in scr3-1 and bit pcr3 4 in pcr3. re 0 1 pcr3 4 01 * pin function p3 4 input pin p3 4 output pin rxd 31 input pin p3 3 /sck 31 the pin function depends on bits cke1, cke0, and smr31 in scr3-1 and bit pcr3 3 in pcr3. cke1 0 1 cke0 0 1 * com3 1 01 ** pcr3 3 01 ** pin function p3 3 input pin p3 3 output pin sck 31 output pin sck 31 input pin p3 2 / reso * pin function p3 2 input pin p3 2 output pin reso output pin p3 1 /ud the pin function depends on bit ud in pmr3 and bit pcr3 1 in pcr3. ud 0 1 pcr3 1 01 * pin function p3 1 input pin p3 1 output pin ud input pin p3 0 /pwm the pin function depends on bit pwm in pmr3 and bit pcr3 0 in pcr3. pwm 0 1 pcr3 0 01 * pin function p3 0 input pin p3 0 output pin pwm output pin * : don t care 147 8.3.4 pin states table 8.10 shows the port 3 pin states in each operating mode. table 8.10 port 3 pin states pins reset sleep subsleep standby watch subactive active p3 7 /aevl p3 6 /aevh p3 5 /txd 31 p3 4 /rxd 31 p3 3 /sck 31 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional p3 2 / reso * a high-level signal is output when the mos pull-up is in the on state. 8.3.5 mos input pull-up port 3 has a built-in mos input pull-up function that can be controlled by software. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr3 n 00 1 pucr3 n 01 * mos input pull-up off on off (n = 7 to 0) * : don t care 148 8.4 port 4 8.4.1 overview port 4 is a 3-bit i/o port and 1-bit input port, configured as shown in figure 8.3. p4 p4 p4 p4 /irq 0 /txd 32 /rxd 32 /sck 32 3 2 1 0 port 4 figure 8.3 port 4 pin configuration 8.4.2 register configuration and description table 8.8 shows the port 4 register configuration. table 8.8 port 4 registers name abbrev. r/w initial value address port data register 4 pdr4 r/w h'f8 h'ffd7 port control register 4 pcr4 w h'f8 h'ffe7 1. port data register 4 (pdr4) b it i nitial value r ead/write 7 1 6 1 5 1 4 1 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 3210 pdr4 is an 8-bit register that stores data for port 4 pins p4 2 to p4 0 . if port 4 is read while pcr4 bits are set to 1, the values stored in pdr4 are read, regardless of the actual pin states. if port 4 is read while pcr4 bits are cleared to 0, the pin states are read. upon reset, pdr4 is initialized to h'f8. 149 2. port control register 4 (pcr4) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w 210 pcr4 is an 8-bit register for controlling whether each of port 4 pins p4 2 to p4 0 functions as an input pin or output pin. setting a pcr4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr4 and pdr4 settings are valid when the corresponding pins are designated for general-purpose input/output by scr3-2. upon reset, pcr4 is initialized to h'f8. pcr4 is a write-only register, which always reads all 1s. 8.4.3 pin functions table 8.9 shows the port 4 pin functions. table 8.9 port 4 pin functions pin pin functions and selection method p4 3 / irq irq * pin function p4 2 input pin p4 2 output pin txd 32 output pin p4 1 /rxd 32 the pin function depends on bit re in scr3-2 and bit pcr4 1 in pcr4. re 32 01 pcr4 1 01 * pin function p4 1 input pin p4 1 output pin rxd 32 input pin * : don t care 150 table 8.9 port 4 pin functions (cont) pin pin functions and selection method p4 0 /sck 32 the pin function depends on bit cke1 and cke0 in scr3-2, bit com32 in smr32, and bit pcr4 0 in pcr4. cke1 0 1 cke0 0 1 * com32 0 1 ** pcr4 0 01 ** pin function p4 0 input pin p4 0 output pin sck 32 output pin sck 32 input pin 8.4.4 pin states table 8.10 shows the port 4 pin states in each operating mode. table 8.10 port 4 pin states pins reset sleep subsleep standby watch subactive active p4 3 /irq 0 p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 151 8.5 port 5 8.5.1 overview port 5 is an 8-bit i/o port, configured as shown in figure 8.4. p5 7 /wkp 7 /seg 8 p5 6 /wkp 6 /seg 7 p5 5 /wkp 5 /seg 6 p5 4 /wkp 4 /seg 5 p5 3 /wkp 3 /seg 4 p5 2 /wkp 2 /seg 3 p5 1 /wkp 1 /seg 2 p5 0 /wkp 0 /seg 1 port 5 figure 8.4 port 5 pin configuration 8.5.2 register configuration and description table 8.11 shows the port 5 register configuration. table 8.11 port 5 registers name abbrev. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd8 port control register 5 pcr5 w h'00 h'ffe8 port pull-up control register 5 pucr5 r/w h'00 h'ffe2 port mode register 5 pmr5 r/w h'00 h'ffcc 152 1. port data register 5 (pdr5) b it i nitial value r ead/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 76543210 pdr5 is an 8-bit register that stores data for port 5 pins p5 7 to p5 0 . if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. upon reset, pdr5 is initialized to h'00. 2. port control register 5 (pcr5) b it i nitial value r ead/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w 76543210 pcr5 is an 8-bit register for controlling whether each of the port 5 pins p5 7 to p5 0 functions as an input pin or output pin. setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr5 and pdr5 settings are valid when the corresponding pins are designated for general-purpose input/output by pmr5 and bits sgs3 to sgs0 in lpcr. upon reset, pcr5 is initialized to h'00. pcr5 is a write-only register, which is always read as all 1s. 3. port pull-up control register 5 (pucr5) b it i nitial value r ead/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 76543210 pucr5 controls whether the mos pull-up of each of port 5 pins p5 7 to p5 0 is on or off. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr5 is initialized to h'00. 153 4. port mode register 5 (pmr5) bit initial value read/write 7 wkp 7 0 r/w 6 wkp 6 0 r/w 5 wkp 5 0 r/w 4 wkp 4 0 r/w 3 wkp 3 0 r/w 0 wkp 0 0 r/w 2 wkp 2 0 r/w 1 wkp 1 0 r/w pmr5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. upon reset, pmr5 is initialized to h'00. bit n: p5 n / wkp n /seg n+1 pin function switch (wkpn) when pin p5n/ wkp n/segn+1 is not used as seg n+1 , these bits select whether the pin is used as p5n or wkp n . bit n wkpn description 0 functions as p5n i/o pin (initial value) 1 functions as wkp 154 8.5.3 pin functions table 8.12 shows the port 5 pin functions. table 8.12 port 5 pin functions pin pin functions and selection method p5 7 / wkp wkp *** 1 *** wkp n 01 * pcr5 n 01 ** pin function p5 n input pin p5 n output pin wkpn * : don t care 8.5.4 pin states table 8.13 shows the port 5 pin states in each operating mode. table 8.13 port 5 pin states pins reset sleep subsleep standby watch subactive active p5 7 / wkp wkp * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 155 8.5.5 mos input pull-up port 5 has a built-in mos input pull-up function that can be controlled by software. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr5 n 00 1 pucr5 n 01 * mos input pull-up off on off (n = 7 to 0) * : don t care 156 8.6 port 6 8.6.1 overview port 6 is an 8-bit i/o port. the port 6 pin configuration is shown in figure 8.5. p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 port 6 figure 8.5 port 6 pin configuration 8.6.2 register configuration and description table 8.14 shows the port 6 register configuration. table 8.14 port 6 registers name abbrev. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd9 port control register 6 pcr6 w h'00 h'ffe9 port pull-up control register 6 pucr6 r/w h'00 h'ffe3 157 1. port data register 6 (pdr6) bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 210 54 76 3 pdr6 is an 8-bit register that stores data for port 6 pins p6 7 to p6 0 . if port 6 is read while pcr6 bits are set to 1, the values stored in pdr6 are read, regardless of the actual pin states. if port 6 is read while pcr6 bits are cleared to 0, the pin states are read. upon reset, pdr6 is initialized to h'00. 2. port control register 6 (pcr6) bit initial value read/write 7 pcr6 7 0 w 6 pcr6 6 0 w 5 pcr6 5 0 w 4 pcr6 4 0 w 3 pcr6 3 0 w 0 pcr6 0 0 w 2 pcr6 2 0 w 1 pcr6 1 0 w pcr6 is an 8-bit register for controlling whether each of the port 6 pins p6 7 to p6 0 functions as an input pin or output pin. setting a pcr6 bit to 1 makes the corresponding pin (p6 7 to p6 0 ) an output pin, while clearing the bit to 0 makes the pin an input pin. pcr6 and pdr6 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr6 is initialized to h'00. pcr6 is a write-only register, which always reads all 1s. 158 3. port pull-up control register 6 (pucr6) b it i nitial value r ead/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 2 10 5 43 76 pucr6 controls whether the mos pull-up of each of the port 6 pins p6 7 to p6 0 is on or off. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr6 is initialized to h'00. 8.6.3 pin functions table 8.15 shows the port 6 pin functions. table 8.15 port 6 pin functions pin pin functions and selection method p6 7 /seg 16 to p6 0 /seg 9 the pin function depends on bit pcr6n in pcr6 and bits sgs3 to sgs0 in lpcr. (n = 7 to 0) seg3 to segs0 00 ** , 010 * 011 ** , 1 *** pcr6 n 01 * pin function p6 n input pin p6 n output pin seg n+9 output pin * : don t care 8.6.4 pin states table 8.16 shows the port 6 pin states in each operating mode. table 8.16 port 6 pin states pin reset sleep subsleep standby watch subactive active p6 7 /seg 16 to p6 0 /seg 9 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 159 8.6.5 mos input pull-up port 6 has a built-in mos pull-up function that can be controlled by software. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr6 n 00 1 pucr6 n 01 * mos input pull-up off on off (n = 7 to 0) * : don t care 160 8.7 port 7 8.7.1 overview port 7 is a 8-bit i/o port, configured as shown in figure 8.6. p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 port 7 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 figure 8.6 port 7 pin configuration 8.7.2 register configuration and description table 8.17 shows the port 7 register configuration. table 8.17 port 7 registers name abbrev. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffda port control register 7 pcr7 w h'00 h'ffea 161 1. port data register 7 (pdr7) bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 76543210 pdr7 is an 8-bit register that stores data for port 7 pins p7 7 to p7 0 . if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read. upon reset, pdr7 is initialized to h'00. 2. port control register 7 (pcr7) bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w 76543210 pcr7 is an 8-bit register for controlling whether each of the port 7 pins p7 7 to p7 0 functions as an input pin or output pin. setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr7 and pdr7 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr7 is initialized to h'00. pcr7 is a write-only register, which always reads as all 1s. 162 8.7.3 pin functions table 8.18 shows the port 7 pin functions. table 8.18 port 7 pin functions pin pin functions and selection method p7 7 /seg 24 to p7 0 /seg 17 the pin function depends on bit pcr7 n in pcr7 and bits sgs3 to sgs0 in lpcr. (n = 7 to 0) segs3 to segs0 00 ** 01 ** , 1 *** pcr7 n 01 * pin function p7 n input pin p7 n output pin seg n+17 output pin * : don t care 8.7.4 pin states table 8.19 shows the port 7 pin states in each operating mode. table 8.19 port 7 pin states pins reset sleep subsleep standby watch subactive active p7 7 /seg 24 to p7 0 /seg 17 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 163 8.8 port 8 8.8.1 overview port 8 is an 8-bit i/o port configured as shown in figure 8.7. p8 7 /seg 32 /cl 1 p8 6 /seg 31 /cl 2 p8 5 /seg 30 /do p8 4 /seg 29 /m p8 3 /seg 28 port 8 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 figure 8.7 port 8 pin configuration 8.8.2 register configuration and description table 8.20 shows the port 8 register configuration. table 8.20 port 8 registers name abbrev. r/w initial value address port data register 8 pdr8 r/w h'00 h'ffdb port control register 8 pcr8 w h'00 h'ffeb 164 1. port data register 8 (pdr8) b it i nitial value r ead/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 76543210 pdr8 is an 8-bit register that stores data for port 8 pins p8 7 to p8 0 . if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. upon reset, pdr8 is initialized to h'00. 2. port control register 8 (pcr8) b it i nitial value r ead/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w 76543210 pcr8 is an 8-bit register for controlling whether each of the port 8 pins p8 7 to p8 0 functions as an input or output pin. setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr8 and pdr8 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr8 is initialized to h'00. pcr8 is a write-only register, which is always read as all 1s. 165 8.8.3 pin functions table 8.21 shows the port 8 pin functions. table 8.21 port 8 pin functions pin pin functions and selection method p8 7 /seg 32 / cl 1 the pin function depends on bit pcr8 7 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** * sgx 0 0 1 pcr8 7 01 ** pin function p8 7 input pin p8 7 output pin seg 32 output pin cl 1 output pin p8 6 /seg 31 / cl 2 the pin function depends on bit pcr8 6 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** * sgx 0 0 1 pcr8 6 01 ** pin function p8 6 input pin p8 6 output pin seg 31 output pin cl 2 output pin p8 5 /seg 30 / do the pin function depends on bit pcr8 5 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** * sgx 0 0 1 pcr9 5 01 ** pin function p8 5 input pin p8 5 output pin seg 30 output pin d0 output pin p8 4 /seg 29 / m the pin function depends on bit pcr8 4 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** * sgx 0 0 1 pcr9 4 01 ** pin function p8 4 input pin p8 4 output pin seg 29 output pin m output pin p8 3 /seg 28 to p8 0 /seg 25 the pin function depends on bit pcr8 n in pcr8 and bits sgs3 to sgs0 in lpcr. (n = 3 to 0) segs3 to segs0 000 * 001 * , 01 ** , 1 *** pcr8 n 01 * pin function p8 n input pin p8 n output pin seg n+25 output pin * : don t care 166 8.8.4 pin states table 8.22 shows the port 8 pin states in each operating mode. table 8.22 port 8 pin states pins reset sleep subsleep standby watch subactive active p8 7 /seg 32 /cl 1 p8 6 /seg 31 /cl 2 p8 5 /seg 30 /do p8 4 /seg 29 /m p8 3 /seg 28 to p8 0 /seg 25 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 167 8.9 port a 8.9.1 overview port a is a 4-bit i/o port, configured as shown in figure 8.8. pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 port a figure 8.8 port a pin configuration 8.9.2 register configuration and description table 8.23 shows the port a register configuration. table 8.23 port a registers name abbrev. r/w initial value address port data register a pdra r/w h'f0 h'ffdd port control register a pcra w h'f0 h'ffed 1. port data register a (pdra) bit initial value read/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 3210 pdra is an 8-bit register that stores data for port a pins pa 3 to pa 0 . if port a is read while pcra bits are set to 1, the values stored in pdra are read, regardless of the actual pin states. if port a is read while pcra bits are cleared to 0, the pin states are read. upon reset, pdra is initialized to h'f0. 168 2. port control register a (pcra) b it i nitial value r ead/write 7 1 6 1 5 1 4 1 3 pcra 0 r/w 0 pcra 0 r/w 2 pcra 0 r/w 1 pcra 0 r/w 3210 pcra controls whether each of port a pins pa 3 to pa 0 functions as an input pin or output pin. setting a pcra bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcra and pdra settings are valid when the corresponding pins are designated for general-purpose input/output by lpcr. upon reset, pcra is initialized to h'f0. pcra is a write-only register, which always reads all 1s. 169 8.9.3 pin functions table 8.24 shows the port a pin functions. table 8.24 port a pin functions pin pin functions and selection method pa 3 /com 4 the pin function depends on bit pcra 3 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 3 01 * pin function pa 3 input pin pa 3 output pin com 4 output pin pa 2 /com 3 the pin function depends on bit pcra 2 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 2 01 * pin function pa 2 input pin pa 2 output pin com 3 output pin pa 1 /com 2 the pin function depends on bit pcra 1 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 1 01 * pin function pa 1 input pin pa 1 output pin com 2 output pin pa 0 /com 1 the pin function depends on bit pcra 0 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 not 0000 pcra 0 01 * pin function pa 0 input pin pa 0 output pin com 1 output pin * : don t care 170 8.9.4 pin states table 8.25 shows the port a pin states in each operating mode. table 8.25 port a pin states pins reset sleep subsleep standby watch subactive active pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 171 8.10 port b 8.10.1 overview port b is an 8-bit input-only port, configured as shown in figure 8.9. pb 7 /an 7 pb 6 /an 6 pb 5 /an 5 pb 4 /an 4 pb 3 /an 3 port b pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 figure 8.9 port b pin configuration 8.10.2 register configuration and description table 8.26 shows the port b register configuration. table 8.26 port b register name abbrev. r/w address port data register b pdrb r h'ffde port data register b (pdrb) bit read/write 7 pb r 6 pb r 5 pb r 4 pb r 3 pb r 0 pb r 2 pb r 1 pb r 32 1 0 7654 reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage. 172 8.11 input/output data inversion function 8.11.1 overview with input pins wkp 0 to wkp 7 , rxd 31 , and rxd 32 , and output pins txd 31 and txd 32 , the data can be handled in inverted form. scinv0 scinv2 rxd 31 rxd 32 p3 4 /rxd 31 p4 1 /rxd 32 scinv1 scinv3 txd 31 txd 32 p3 5 /txd 31 p4 2 /txd 32 figure 8.10 input/output data inversion function 8.11.2 register configuration and descriptions table 8.27 shows the registers used by the input/output data inversion function. table 8.27 register configuration name abbreviation r/w address serial port control register spcr r/w h'ff91 serial port control register (spcr) bit initial value read/write 7 1 6 1 5 spc32 0 r/w 4 spc31 0 r/w 3 scinv3 0 r/w 0 scinv0 0 r/w 2 scinv2 0 r/w 1 scinv1 0 r/w spcr is an 8-bit readable/writable register that performs rxd 31 , rxd 32 , txd 31 , and txd 32 pin input/output data inversion switching. spcr is initialized to h'c0 by a reset. 173 bit 0: rxd 31 pin input data inversion switch bit 0 specifies whether or not rxd 31 pin input data is to be inverted. bit 0 scinv0 description 0 rxd 31 input data is not inverted (initial value) 1 rxd 31 input data is inverted bit 1: txd 31 pin output data inversion switch bit 1 specifies whether or not txd 31 pin output data is to be inverted. bit 1 scinv1 description 0 txd 31 output data is not inverted (initial value) 1 txd 31 output data is inverted bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted. bit 2 scinv2 description 0 rxd 32 input data is not inverted (initial value) 1 rxd 32 input data is inverted bit 3: txd 32 pin output data inversion switch bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0 txd 32 output data is not inverted (initial value) 1 txd 32 output data is inverted 174 bit 4: p3 5 /txd 31 pin function switch (spc31) this bit selects whether pin p3 5 /txd 31 is used as p3 5 or as txd 31 . bit 4 spc31 description 0 functions as p3 5 i/o pin (initial value) 1 functions as txd 31 output pin * note: * set the te bit in scr3 after setting this bit to 1. bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. 8.11.3 note on modification of serial port control register when a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. when modifying a serial port control register, do so in a state in which data changes are invalidated. 175 section 9 timers 9.1 overview the h8/3864 series provides six timers: timers a, c, f, g, and a watchdog timer, and an asynchronous event counter. the functions of these timers are outlined in table 9.1. table 9.1 timer functions name functions internal clock event input pin waveform output pin remarks timer a ? 8-bit interval timer ?8 to ?8192 ? interval function (8 choices) ? time base w /128 (choice of 4 overflow periods) ? clock output ?4 to ?32 w , w /4 to w /32 (9 choices) tmow timer c ? 8-bit timer ? interval function ? event counting function ? up-count/down- count selectable ?4 to ?8192, w /4 (7 choices) tmic up-count/down- count controllable by software or hardware timer f 16-bit timer event counting function also usable as two independent8- bit timers output compare output function ?4 to ?32, w /4 (4 choices) tmif tmofl tmofh timer g ? 8-bit timer ? input capture function ? interval function ?2 to ?64, w /4 (4 choices) tmig ? counter clearing option ? built-in capture input signal noise canceler 176 table 9.1 timer functions (cont) name functions internal clock event input pin waveform output pin remarks watchdog timer ? reset signal generated when8- bit counter overflows ?8192 w /32 asynchro- nous event counter ? 16-bit counter ? also usable as two independent 8-bit counters ? counts events asynchronous to and ? aevl aevh 177 9.2 timer a 9.2.1 overview timer a is an 8-bit timer with interval timing and real-time clock time-base functions. the clock time-base function is available when a 32.768-khz crystal oscillator is connected. a clock signal divided from 32.768 khz, from 38.4 khz (if a 38.4 khz crystal oscillator is connected), or from the system clock, can be output at the tmow pin. 1. features features of timer a are given below. ? choice of eight internal clock sources (?8192, ?4096, ?2048, ?512, ?256, ?128, ?32, ?8). ? choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator). ? an interrupt is requested when the counter overflows. ? any of nine clock signals can be output at the tmow pin: 32.768 khz divided by 32, 16, 8, or 4 (1 khz, 2 khz, 4 khz, 8 khz) or 38.4 khz divided by 32, 16, 8, or 4 (1.2 khz, 2.4 khz, 4.8 khz, 9.6 khz), and the system clock divided by 32, 16, 8, or 4. ? use of module standby mode enables this module to be placed in standby mode independently when not used. 178 2. block diagram figure 9.1 shows a block diagram of timer a. psw internal data bus pss notation: tmow 1/4 tma cwors tca w /32 w /16 w /8 w /4 /32 /16 /8 /4 /128 w /8192, /4096, /2048, /512, /256, /128, /32, /8 irrta 8 * 64 * 128 * 256 * /4 w tma: tca: irrta: psw: pss: cwosr: note: * can be selected only when the prescaler w output ( w /128) is used as the tca input clock. timer mode register a timer counter a timer a overflow interrupt request flag prescaler w prescaler s subclock output select register w figure 9.1 block diagram of timer a 3. pin configuration table 9.2 shows the timer a pin configuration. table 9.2 pin configuration name abbrev. i/o function clock output tmow output output of waveform generated by timer a output circuit 179 4. register configuration table 9.3 shows the register configuration of timer a. table 9.3 timer a registers name abbrev. r/w initial value address timer mode register a tma r/w h'10 h'ffb0 timer counter a tca r h'00 h'ffb1 clock stop register 1 ckstpr1 r/w h'ff h'fffa subclock output select register cwosr r/w h'fe h'ff92 9.2.2 register descriptions 1. timer mode register a (tma) bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 4 1 3 tma3 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w tma is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. upon reset, tma is initialized to h'10. 180 bits 7 to 5: clock output select (tma7 to tma5) bits 7 to 5 choose which of eight clock signals is output at the tmow pin. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz or 38.4 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. w is output in all modes except the reset state. cwosr tma cwos bit 7 tma7 bit 6 tma6 bit 5 tma5 clock output 0000 /32 (initial value) 1 /16 10 /8 1 /4 10 0 w /32 1 w /16 10 w /8 1 w /4 1 ** * w * : don t care bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified. 181 bits 3 to 0: internal clock select (tma3 to tma0) bits 3 to 0 select the clock input to tca. the selection is made as follows. description bit 3 tma3 bit 2 tma2 bit 1 tma1 bit 0 tma0 prescaler and divider ratio or overflow period function 0 0 0 0 pss, /8192 (initial value) interval timer 1 pss, /4096 1 0 pss, /2048 1 pss, /512 1 0 0 pss, /256 1 pss, /128 1 0 pss, /32 1 pss, /8 1 0 0 0 psw, 1 s clock time 1 psw, 0.5 s base 1 0 psw, 0.25 s (when using 1 psw, 0.03125 s 32.768 khz) 1 0 0 psw and tca are reset 1 10 1 182 2. timer counter a (tca) b it i nitial value r ead/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 of tma to 11. upon reset, tca is initialized to h'00. 3. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer a is described here. for details of the other bits, see the sections on the relevant modules. bit 0: timer a module standby mode control (tackstp) bit 0 controls setting and clearing of module standby mode for timer a. tackstp description 0 timer a is set to module standby mode 1 timer a module standby mode is cleared (initial value) 183 subclock output select register (cwosr) cwos 76543210 1 1111110 r r r r/w rrr r bit: initial value: read/write: cwosr is an 8-bit read/write register that selects the clock to be output from the tmow pin. cwosr is initialized to h'fe by a reset. bits 7 to 1: reserved bits bits 7 to 1 are reserved; they are always read as 1 and cannot be modified. bit 0: tmow pin clock select (cwos) bit 0 selects the clock to be output from the tmow pin. bit 0 cwos description 0 clock output from timer a is output (see tma) (initial value) 1 w is output 9.2.3 timer operation 1. interval timer operation when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested.* at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see 3.3, interrupts. 184 2. real-time clock time base operation when bit tma3 in tma is set to 1, timer a functions as a real-time clock time base by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to their initial values of h'00. 3. clock output setting bit tmow in port mode register 1 (pmr1) to 1 causes a clock signal to be output at pin tmow. nine different clock output signals can be selected by means of bits tma7 to tma5 in tma and bit cwos in cwosr. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz or 38.4 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, watch mode, subactive mode, and subsleep mode. the 32.768 khz or 38.4 khz clock is output in all modes except the reset state. 9.2.4 timer a operation states table 9.4 summarizes the timer a operation states. table 9.4 timer a operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tca interval reset functions functions halted halted halted halted halted clock time base reset functions functions functions functions functions halted halted tma reset functions retained retained functions retained retained retained note: when the real-time clock time base function is selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ (s) in the count cycle. 185 9.3 timer c 9.3.1 overview timer c is an 8-bit timer that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer c are given below. ? /8192, /2048, /512, /64, /16, /4, w/4) or an external clock (can be used to count external events). ? ? ? w/4 is selected as the internal clock, or when an external clock is selected. ? 186 2. block diagram figure 9.2 shows a block diagram of timer c. ud tmic w /4 pss tmc internal data bus tcc tlc irrtc notation: tmc tcc tlc irrtc pss : timer mode register c : timer counter c : timer load register c : timer c overflow interrupt request flag : prescaler s figure 9.2 block diagram of timer c 187 3. pin configuration table 9.5 shows the timer c pin configuration. table 9.5 pin configuration name abbrev. i/o function timer c event input tmic input input pin for event input to tcc timer c up/down-count selection ud input timer c up/down select 4. register configuration table 9.6 shows the register configuration of timer c. table 9.6 timer c registers name abbrev. r/w initial value address timer mode register c tmc r/w h'18 h'ffb4 timer counter c tcc r h'00 h'ffb5 timer load register c tlc w h'00 h'ffb5 clock stop register 1 ckstpr1 r/w h'ff h'fffa 9.3.2 register descriptions 1. timer mode register c (tmc) bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 4 1 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w tmc is an 8-bit read/write register for selecting the auto-reload function and input clock, and performing up/down-counter control. upon reset, tmc is initialized to h'18. 188 bit 7: auto-reload function select (tmc7) bit 7 selects whether timer c is used as an interval timer or auto-reload timer. bit 7 tmc7 description 0 interval timer function selected (initial value) 1 auto-reload function selected bits 6 and 5: counter up/down control (tmc6, tmc5) selects whether tcc up/down control is performed by hardware using ud pin input, or whether tcc functions as an up-counter or a down-counter. bit 6 tmc6 bit 5 tmc5 description 0 0 tcc is an up-counter (initial value) 0 1 tcc is a down-counter 1 * hardware control by ud pin input ud pin input high: down-counter ud pin input low: up-counter * : don t care bits 4 and 3: reserved bits bits 4 and 3 are reserved; they are always read as 1 and cannot be modified. 189 bits 2 to 0: clock select (tmc2 to tmc0) bits 2 to 0 select the clock input to tcc. for external event counting, either the rising or falling edge can be selected. bit 2 tmc2 bit 1 tmc1 bit 0 tmc0 description 0 0 0 internal clock: /8192 (initial value) 0 0 1 internal clock: /2048 0 1 0 internal clock: /512 0 1 1 internal clock: /64 1 0 0 internal clock: /16 1 0 1 internal clock: /4 1 1 0 internal clock: w/4 1 1 1 external event (tmic): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg1 in the irq edge select register (iegr). see 1. irq edge select register (iegr) in 3.3.2 for details. irq2 must be set to 1 in port mode register 1 (pmr1) before setting 111 in bits tmc2 to tmc0. 2. timer counter c (tcc) bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r tcc is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. the clock source for input to this counter is selected by bits tmc2 to tmc0 in timer mode register c (tmc). tcc values can be read by the cpu at any time. when tcc overflows from h'ff to h'00 or to the value set in tlc, or underflows from h'00 to h'ff or to the value set in tlc, the irrtc bit in irr2 is set to 1. tcc is allocated to the same address as tlc. upon reset, tcc is initialized to h'00. 190 3. timer load register c (tlc) b it i nitial value r ead/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w tlc is an 8-bit write-only register for setting the reload value of timer counter c (tcc). when a reload value is set in tlc, the same value is loaded into timer counter c as well, and tcc starts counting up from that value. when tcc overflows or underflows during operation in auto- reload mode, the tlc value is loaded into tcc. accordingly, overflow/underflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlc as to tcc. upon reset, tlc is initialized to h'00. 4. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer c is described here. for details of the other bits, see the sections on the relevant modules. bit 1: timer c module standby mode control (tcckstp) bit 1 controls setting and clearing of module standby mode for timer c. tcckstp description 0 timer c is set to module standby mode 1 timer c module standby mode is cleared (initial value) 191 9.3.3 timer operation 1. interval timer operation when bit tmc7 in timer mode register c (tmc) is cleared to 0, timer c functions as an 8-bit interval timer. upon reset, tcc is initialized to h'00 and tmc to h'18, so tcc continues up-counting as an interval up-counter without halting immediately after a reset. the timer c operating clock is selected from seven internal clock signals output by prescalers s and w, or an external clock input at pin tmic. the selection is made by bits tmc2 to tmc0 in tmc. tcc up/down-count control can be performed either by software or hardware. the selection is made by bits tmc6 and tmc5 in tmc. after the count value in tcc reaches h'ff (h'00), the next clock input causes timer c to overflow (underflow), setting bit irrtc to 1 in irr2. if ientc = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested. at overflow (underflow), tcc returns to h'00 (h'ff) and starts counting up (down) again. during interval timer operation (tmc7 = 0), when a value is set in timer load register c (tlc), the same value is set in tcc. note: for details on interrupts, see 3.3, interrupts. 192 2. auto-reload timer operation setting bit tmc7 in tmc to 1 causes timer c to function as an 8-bit auto-reload timer. when a reload value is set in tlc, the same value is loaded into tcc, becoming the value from which tcc starts its count. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow/underflow. the tlc value is then loaded into tcc, and the count continues from that value. the overflow/underflow period can be set within a range from 1 to 256 input clocks, depending on the tlc value. the clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmc7 = 1), when a new value is set in tlc, the tlc value is also set in tcc. 3. event counter operation timer c can operate as an event counter, counting rising or falling edges of an external event signal input at pin tmic. external event counting is selected by setting bits tmc2 to tmc0 in timer mode register c to all 1s (111). when timer c is used to count external event input, , bit irq2 in pmr1 should be set to 1 and bit ien2 in ienr1 cleared to 0 to disable interrupt irq 2 requests. 4. tcc up/down control by hardware with timer c, tcc up/down control can be performed by ud pin input. when bit tmc6 is set to 1 in tmc, tcc functions as an up-counter when ud pin input is high, and as a down-counter when low. when using ud pin input, set bit ud to 1 in pmr3. 193 9.3.4 timer c operation states table 9.7 summarizes the timer c operation states. table 9.7 timer c operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tcc interval reset functions functions halted functions/ halted * functions/ halted * halted halted auto reload reset functions functions halted functions/ halted * functions/ halted * halted halted tmc reset functions retained retained functions retained retained retained note: * when w/4 is selected as the tcc internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode or subsleep mode, either select w/4 as the internal clock or select an external clock. the counter will not operate on any other internal clock. if w/4 is selected as the internal clock for the counter when w/8 has been selected as subclock sub , the lower 2 bits of the counter operate on the same cycle, and the operation of the least significant bit is unrelated to the operation of the counter. 194 9.4 timer f 9.4.1 overview timer f is a 16-bit timer with a built-in output compare function. as well as counting external events, timer f also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. timer f can also be used as two independent 8-bit timers (timer fh and timer fl). 1. features features of timer f are given below. ? /32, /16, /4, w/4) or an external clock (can be used as an external event counter) ? ? ? ? timer fh 8-bit timer * timer fl 8-bit timer/event counter internal clock choice of 4 ( /32, /16, /4, w/4) event input tmif pin toggle output one compare match signal, output to tmofh pin(initial value settable) one compare match signal, output to tmofl pin (initial value settable) counter reset counter can be reset by compare match signal interrupt sources one compare match one overflow note: * when timer f operates as a 16-bit timer, it operates on the timer fl overflow signal. ? w/4 is selected as the internal clock, timer f can operate in watch mode, subactive mode, and subsleep mode. ? 195 2. block diagram figure 9.3 shows a block diagram of timer f. pss toggle circuit toggle circuit tmif w /4 tmofl tmofh tcrf tcfl ocrfl tcfh ocrfh tcsrf comparator comparator match irrtfh irrtfl notation: tcrf: tcsrf: tcfh: tcfl: ocrfh: ocrfl: irrtfh: irrtfl: pss: timer control register f timer control/status register f 8-bit timer counter fh 8-bit timer counter fl output compare register fh output compare register fl timer fh interrupt request flag timer fl interrupt request flag prescaler s internal data bus figure 9.3 block diagram of timer f 196 3. pin configuration table 9.8 shows the timer f pin configuration. table 9.8 pin configuration name abbrev. i/o function timer f event input tmif input event input pin for input to tcfl timer fh output tmofh output timer fh toggle output pin timer fl output tmofl output timer fl toggle output pin 4. register configuration table 9.9 shows the register configuration of timer f. table 9.9 timer f registers name abbrev. r/w initial value address timer control register f tcrf w h'00 h'ffb6 timer control/status register f tcsrf r/w h'00 h'ffb7 8-bit timer counter fh tcfh r/w h'00 h'ffb8 8-bit timer counter fl tcfl r/w h'00 h'ffb9 output compare register fh ocrfh r/w h'ff h'ffba output compare register fl ocrfl r/w h'ff h'ffbb clock stop register 1 ckstpr1 r/w h'ff h'fffa 197 9.4.2 register descriptions 1. 16-bit timer counter (tcf) 8-bit timer counter (tcfh) 8-bit timer counter (tcfl) 15 14 13 12 11 10 9 8 tcf tcfh tcfl 76543210 0000000000000000 r/w bit: initial value: read/write: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcf is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters tcfh and tcfl. in addition to the use of tcf as a 16-bit counter with tcfh as the upper 8 bits and tcfl as the lower 8 bits, tcfh and tcfl can also be used as independent 8-bit counters. tcfh and tcfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see 9.4.3, cpu interface. tcfh and tcfl are each initialized to h'00 upon reset. a. 16-bit mode (tcf) when cksh2 is cleared to 0 in tcrf, tcf operates as a 16-bit counter. the tcf input clock is selected by bits cksl2 to cksl0 in tcrf. tcf can be cleared in the event of a compare match by means of cclrh in tcsrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf is 1 at this time, irrtfh is set to 1 in irr2, and if ientfh in ienr2 is 1, an interrupt request is sent to the cpu. b. 8-bit mode (tcfl/tcfh) when cksh2 is set to 1 in tcrf, tcfh and tcfl operate as two independent 8-bit counters. the tcfh (tcfl) input clock is selected by bits cksh2 to cksh0 (cksl2 to cksl0) in tcrf. tcfh (tcfl) can be cleared in the event of a compare match by means of cclrh (cclrl) in tcsrf. when tcfh (tcfl) overflows from h'ff to h'00, ovfh (ovfl) is set to 1 in tcsrf. if ovieh (oviel) in tcsrf is 1 at this time, irrtfh (irrtfl) is set to 1 in irr2, and if ientfh (ientfl) in ienr2 is 1, an interrupt request is sent to the cpu. 198 2. 16-bit output compare register (ocrf) 8-bit output compare register (ocrfh) 8-bit output compare register (ocrfl) 15 14 13 12 11 10 9 8 ocrf ocrfh ocrfl 76543210 1111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ocrf is a 16-bit read/write register composed of the two registers ocrfh and ocrfl. in addition to the use of ocrf as a 16-bit register with ocrfh as the upper 8 bits and ocrfl as the lower 8 bits, ocrfh and ocrfl can also be used as independent 8-bit registers. ocrfh and ocrfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see 9.4.3, cpu interface. ocrfh and ocrfl are each initialized to h'ff upon reset. a. 16-bit mode (ocrf) when cksh2 is cleared to 0 in tcrf, ocrf operates as a 16-bit register. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. at the same time, irrtfh is set to 1 in irr2. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin by means of compare matches, and the output level can be set (high or low) by means of tolh in tcrf. b. 8-bit mode (ocrfh/ocrfl) when cksh2 is set to 1 in tcrf, ocrfh and ocrfl operate as two independent 8-bit registers. ocrfh contents are compared with tcfh, and ocrfl contents are with tcfl. when the ocrfh (ocrfl) and tcfh (tcfl) values match, cmfh (cmfl) is set to 1 in tcsrf. at the same time, irrtfh (irrtfl) is set to 1 in irr2. if ientfh (ientfl) in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin (tmofl pin) by means of compare matches, and the output level can be set (high or low) by means of tolh (toll) in tcrf. 199 3. timer control register f (tcrf) tolh cksl2 cksl1 cksl0 cksh2 cksh1 cksh0 toll 76543210 0 0000000 w www www w bit: initial value: read/write: tcrf is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the tmofh and tmofl pins. tcrf is initialized to h'00 upon reset. bit 7: toggle output level h (tolh) bit 7 sets the tmofh pin output level. the output level is effective immediately after this bit is written. bit 7 tolh description 0 low level (initial value) 1 high level bits 6 to 4: clock select h (cksh2 to cksh0) bits 6 to 4 select the clock input to tcfh from among four internal clock sources or tcfl overflow. bit 6 cksh2 bit 5 cksh1 bit 4 cksh0 description 0 0 0 16-bit mode, counting on tcfl overflow signal (initial value) 001 010 0 1 1 use prohibited 1 0 0 internal clock: counting on /32 1 0 1 internal clock: counting on /16 1 1 0 internal clock: counting on /4 1 1 1 internal clock: counting on w/4 * : don t care 200 bit 3: toggle output level l (toll) bit 3 sets the tmofl pin output level. the output level is effective immediately after this bit is written. bit 3 toll description 0 low level (initial value) 1 high level bits 2 to 0: clock select l (cksl2 to cksl0) bits 2 to 0 select the clock input to tcfl from among four internal clock sources or external event input. bit 2 cksl2 bit 1 cksl1 bit 0 cksl0 description 0 0 0 counting on external event (tmif) rising/ (initial value) 0 0 1 falling edge * 010 0 1 1 use prohibited 1 0 0 internal clock: counting on /32 1 0 1 internal clock: counting on /16 1 1 0 internal clock: counting on /4 1 1 1 internal clock: counting on w/4 note: * external event edge selection is set by ieg3 in the irq edge select register (iegr). for details, see 1. irq edge select register (iegr) in section 3.3.2. note that the timer f counter may increment if the setting of irq3 in port mode register 1 (pmr1) is changed from 0 to 1 while the tmif pin is low in order to change the tmif pin function. 201 4. timer control/status register f (tcsrf) ovfh cmfl oviel cclrl cmfh ovieh cclrh ovfl 76543210 0 0000000 r/w * r/w * r/w r/w r/w * r/w r/w r/w * note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. bit: initial value: read/write: tcsrf is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. tcsrf is initialized to h'00 upon reset. bit 7: timer overflow flag h (ovfh) bit 7 is a status flag indicating that tcfh has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 ovfh description 0 clearing conditions: (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting conditions: set when tcfh overflows from h ff to h 00 bit 6: compare match flag h (cmfh) bit 6 is a status flag indicating that tcfh has matched ocrfh. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 cmfh description 0 clearing conditions: (initial value) after reading cmfh = 1, cleared by writing 0 to cmfh 1 setting conditions: set when the tcfh value matches the ocrfh value 202 bit 5: timer overflow interrupt enable h (ovieh) bit 5 selects enabling or disabling of interrupt generation when tcfh overflows. bit 5 ovieh description 0 tcfh overflow interrupt request is disabled (initial value) 1 tcfh overflow interrupt request is enabled bit 4: counter clear h (cclrh) in 8-bit mode, bit 4 selects whether tcf is cleared when tcf and ocrf match. in 8-bit mode, bit 4 selects whether tcfh is cleared when tcfh and ocrfh match. bit 4 cclrh description 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled (initial value) 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled bit 3: timer overflow flag l (ovfl) bit 3 is a status flag indicating that tcfl has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 3 ovfl description 0 clearing conditions: (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting conditions: set when tcfl overflows from h ff to h 00 203 bit 2: compare match flag l (cmfl) bit 2 is a status flag indicating that tcfl has matched ocrfl. this flag is set by hardware and cleared by software. it cannot be set by software. bit 2 cmfl description 0 clearing conditions: (initial value) after reading cmfl = 1, cleared by writing 0 to cmfl 1 setting conditions: set when the tcfl value matches the ocrfl value bit 1: timer overflow interrupt enable l (oviel) bit 1 selects enabling or disabling of interrupt generation when tcfl overflows. bit 1 oviel description 0 tcfl overflow interrupt request is disabled (initial value) 1 tcfl overflow interrupt request is enabled bit 0: counter clear l (cclrl) bit 0 selects whether tcfl is cleared when tcfl and ocrfl match. bit 0 cclrl description 0 tcfl clearing by compare match is disabled (initial value) 1 tcfl clearing by compare match is enabled 204 5. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer f is described here. for details of the other bits, see the sections on the relevant modules. bit 2: timer f module standby mode control (tfckstp) bit 2 controls setting and clearing of module standby mode for timer f. tfckstp description 0 timer f is set to module standby mode 1 timer f module standby mode is cleared (initial value) 205 9.4.3 cpu interface tcf and ocrf are 16-bit read/write registers, but the cpu is connected to the on-chip peripheral modules by an 8-bit data bus. when the cpu accesses these registers, it therefore uses an 8-bit temporary register (temp). in 16-bit mode, tcf read/write access and ocrf write access must be performed 16 bits at a time (using two consecutive byte-size mov instructions), and the upper byte must be accessed before the lower byte. data will not be transferred correctly if only the upper byte or only the lower byte is accessed. in 8-bit mode, there are no restrictions on the order of access. 1. write access write access to the upper byte results in transfer of the upper-byte write data to temp. next, write access to the lower byte results in transfer of the data in temp to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. 206 figure 9.4 shows an example in which h'aa55 is written to tcf. w rite to upper byte cpu (h'aa) temp (h'aa) tcfh ( ) tcfl ( ) bus interface module data bus w rite to lower byte cpu (h'55) temp (h'aa) tcfh (h'aa) tcfl (h'55) bus interface module data bus figure 9.4 write access to tcr (cpu tcf) 207 2. read access in access to tcf, when the upper byte is read the upper-byte data is transferred directly to the cpu and the lower-byte data is transferred to temp. next, when the lower byte is read, the lower-byte data in temp is transferred to the cpu. in access to ocrf, when the upper byte is read the upper-byte data is transferred directly to the cpu. when the lower byte is read, the lower-byte data is transferred directly to the cpu. figure 9.5 shows an example in which tcf is read when it contains h'aaff. read upper byte cpu (h'aa) temp (h'ff) tcfh (h'aa) tcfl (h'ff) bus interface module data bus read lower byte cpu (h'ff) temp (h'ff) tcfh (ab)* tcfl (00)* bus interface module data bus note: * h'ab00 if counter has been updated once. figure 9.5 read access to tcf (tcf cpu) 208 9.4.4 operation timer f is a 16-bit counter that increments on each input clock pulse. the timer f value is constantly compared with the value set in output compare register f, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. timer f can also function as two independent 8-bit timers. 1. timer f operation timer f has two operating modes, 16-bit timer mode and 8-bit timer mode. the operation in each of these modes is described below. a. operation in 16-bit timer mode when cksh2 is cleared to 0 in timer control register f (tcrf), timer f operates as a 16-bit timer. following a reset, timer counter f (tcf) is initialized to h'0000, output compare register f (ocrf) to h'ffff, and timer control register f (tcrf) and timer control/status register f (tcsrf) to h'00. the counter starts incrementing on external event (tmif) input. the external event edge selection is set by ieg3 in the irq edge select register (iegr). the timer f operating clock can be selected from four internal clocks output by prescaler s or an external clock by means of bits cksl2 to cksl0 in tcrf. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu, and at the same time, tmofh pin output is toggled. if cclrh in tcsrf is 1, tcf is cleared. tmofh pin output can also be set by tolh in tcrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf and ientfh in ienr2 are both 1, an interrupt request is sent to the cpu. b. operation in 8-bit timer mode when cksh2 is set to 1 in tcrf, tcf operates as two independent 8-bit timers, tcfh and tcfl. the tcfh/tcfl input clock is selected by cksh2 to cksh0/cksl2 to cksl0 in tcrf. when the ocrfh/ocrfl and tcfh/tcfl values match, cmfh/cmfl is set to 1 in tcsrf. if ientfh/ientfl in ienr2 is 1, an interrupt request is sent to the cpu, and at the same time, tmofh pin/tmofl pin output is toggled. if cclrh/cclrl in tcsrf is 1, tcfh/tcfl is cleared. tmofh pin/tmofl pin output can also be set by tolh/toll in tcrf. when tcfh/tcfl overflows from h'ff to h'00, ovfh/ovfl is set to 1 in tcsrf. if ovieh/oviel in tcsrf and ientfh/ientfl in ienr2 are both 1, an interrupt request is sent to the cpu. 209 2. tcf increment timing tcf is incremented by clock input (internal clock or external event input). a. internal clock operation bits cksh2 to cksh0 or cksl2 to cksl0 in tcrf select one of four internal clock sources ( /32, /16, /4, or w/4) created by dividing the system clock ( or w). b. external event operation external event input is selected by clearing cksl2 to 0 in tcrf. tcf can increment on either the rising or falling edge of external event input. external event edge selection is set by ieg3 in the interrupt controller s iegr register. an external event pulse width of at least 2 system clocks ( ) is necessary. shorter pulses will not be counted correctly. 3. tmofh/tmofl output timing in tmofh/tmofl output, the value set in tolh/toll in tcrf is output. the output is toggled by the occurrence of a compare match. figure 9.6 shows the output timing. tmif (when ieg3 = 1) count input clock tcf ocrf tmofh tmofl compare match signal nn n n n+1 n+1 figure 9.6 tmofh/tmofl output timing 210 4. tcf clear timing tcf can be cleared by a compare match with ocrf. 5. timer overflow flag (ovf) set timing ovf is set to 1 when tcf overflows from h'ffff to h'0000. 6. compare match flag set timing the compare match flag (cmfh or cmfl) is set to 1 when the tcf and ocrf values match. the compare match signal is generated in the last state during which the values match (when tcf is updated from the matching value to a new value). when tcf matches ocrf, the compare match signal is not generated until the next counter clock. 7. timer f operation modes timer f operation modes are shown in table 9.10. table 9.10 timer f operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby tcf reset functions functions functions/ halted * functions/ halted * functions/ halted * halted halted ocrf reset functions held held functions held held held tcrf reset functions held held functions held held held tcsrf reset functions held held functions held held held note: * when w /4 is selected as the tcf internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode, watch mode, or subsleep mode, w /4 must be selected as the internal clock. the counter will not operate if any other internal clock is selected. 211 9.4.5 application notes the following types of contention and operation can occur when timer f is used. 1. 16-bit timer mode in toggle output, tmofh pin output is toggled when all 16 bits match and a compare match signal is generated. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. tmofl pin output is unstable in 16-bit mode, and should not be used; the tmofl pin should be used as a port pin. if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. compare match flag cmfh is set when all 16 bits match and a compare match signal is generated. compare match flag cmfl is set if the setting conditions for the lower 8 bits are satisfied. when tcf overflows, ovfh is set. ovfl is set if the setting conditions are satisfied when the lower 8 bits overflow. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 2. 8-bit timer mode a. tcfh, ocrfh in toggle output, tmofh pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. if an ocrfh write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfh clock. if a tcfh write and overflow signal output occur simultaneously, the overflow signal is not output. b. tcfl, ocrfl in toggle output, tmofl pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, toll data is output to the tmofl pin as a result of the tcrf write. 212 if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 213 9.5 timer g 9.5.1 overview timer g is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). high-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle. if input capture input is not set, timer g functions as an 8-bit interval timer. 1. features features of timer g are given below. ? /64, /32, /2, w/2) ? ? ? ? ? ? w/2 is selected as the internal clock. ? 214 2. block diagram figure 9.7 shows a block diagram of timer g. pss tmg icrgf tcg icrgr noise canceler edge detector level detector irrtg w/4 tmig ncs n otation: tmg tcg icrgf icrgr irrtg ncs pss : timer mode register g : timer counter g : input capture register gf : input capture register gr : timer g interrupt request flag : noise canceler select : prescaler s internal data bus figure 9.7 block diagram of timer g 215 3. pin configuration table 9.11 shows the timer g pin configuration. table 9.11 pin configuration name abbrev. i/o function input capture input tmig input input capture input pin 4. register configuration table 9.12 shows the register configuration of timer g. table 9.12 timer g registers name abbrev. r/w initial value address timer control register g tmg r/w h'00 h'ffbc timer counter g tcg h'00 input capture register gf icrgf r h'00 h'ffbd input capture register gr icrgr r h'00 h'ffbe clock stop register 1 ckstpr1 r/w h'ff h'fffa 216 9.5.2 register descriptions 1. timer counter (tcg) tcg7 tcg2 tcg1 tcg0 tcg6 tcg5 tcg4 tcg3 76543210 0 0000000 bit: initial value: read/write: tcg is an 8-bit up-counter which is incremented by clock input. the input clock is selected by bits cks1 and cks0 in tmg. tmig in pmr1 is set to 1 to operate tcg as an input capture timer, or cleared to 0 to operate tcg as an interval timer*. in input capture timer operation, the tcg value can be cleared by the rising edge, falling edge, or both edges of the input capture input signal, according to the setting made in tmg. when tcg overflows from h'ff to h'00, if ovie in tmg is 1, irrtg is set to 1 in irr2, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see 3.3, interrupts. tcg cannot be read or written by the cpu. it is initialized to h'00 upon reset. note: * an input capture signal may be generated when tmig is modified. 2. input capture register gf (icrgf) icrgf7 icrgf2 icrgf1 icrgf0 icrgf6 icrgf5 icrgf4 icrgf3 76543210 0 0000000 r rrr rrr r bit: initial value: read/write: icrgf is an 8-bit read-only register. when a falling edge of the input capture input signal is detected, the current tcg value is transferred to icrgf. if iiegs in tmg is 1 at this time, irrtg is set to 1 in irr2, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see 3.3, interrupts. to ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2 sub (when the noise canceler is not used). icrgf is initialized to h'00 upon reset. 217 3. input capture register gr (icrgr) icrgr7 icrgr2 icrgr1 icrgr0 icrgr6 icrgr5 icrgr4 icrgr3 76543210 0 0000000 r rrr rrr r bit: initial value: read/write: icrgr is an 8-bit read-only register. when a rising edge of the input capture input signal is detected, the current tcg value is transferred to icrgr. if iiegs in tmg is 1 at this time, irrtg is set to 1 in irr2, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see 3.3, interrupts. to ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2 sub (when the noise canceler is not used). icrgr is initialized to h'00 upon reset. 4. timer mode register g (tmg) ovfh cclr0 cks1 cks0 ovfl ovie iiegs cclr1 76543210 0 0000000 r/w * r/w r/w r/w r/w * r/w r/w r/w bit: initial value: read/write: note: * bits 7 and 6 can only be written with 0, for flag clearing. tmg is an 8-bit read/write register that performs tcg clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags. tmg is initialized to h'00 upon reset. 218 bit 7: timer overflow flag h (ovfh) bit 7 is a status flag indicating that tcg has overflowed from h'ff to h'00 when the input capture input signal is high. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 ovfh description 0 clearing conditions: (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting conditions: set when tcg overflows from h'ff to h'00 bit 6: timer overflow flag l (ovfl) bit 6 is a status flag indicating that tcg has overflowed from h'ff to h'00 when the input capture input signal is low, or in interval operation. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 ovfl description 0 clearing conditions: (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting conditions: set when tcg overflows from h'ff to h'00 bit 5: timer overflow interrupt enable (ovie) bit 5 selects enabling or disabling of interrupt generation when tcg overflows. bit 5 ovie description 0 tcg overflow interrupt request is disabled (initial value) 1 tcg overflow interrupt request is enabled 219 bit 4: input capture interrupt edge select (iiegs) bit 4 selects the input capture input signal edge that generates an interrupt request. bit 4 iiegs description 0 interrupt generated on rising edge of input capture input signal (initial value) 1 interrupt generated on falling edge of input capture input signal bits 3 and 2: counter clear 1 and 0 (cclr1, cclr0) bits 3 and 2 specify whether or not tcg is cleared by the rising edge, falling edge, or both edges of the input capture input signal. bit 3 cclr1 bit 2 cclr0 description 0 0 tcg clearing is disabled (initial value) 0 1 tcg cleared by falling edge of input capture input signal 1 0 tcg cleared by rising edge of input capture input signal 1 1 tcg cleared by both edges of input capture input signal bits 1 and 0: clock select (cks1, cks0) bits 1 and 0 select the clock input to tcg from among four internal clock sources. bit 1cks1 bit 0cks0 description 0 0 internal clock: counting on /64 (initial value) 0 1 internal clock: counting on /32 1 0 internal clock: counting on /2 1 1 internal clock: counting on w/4 220 5. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer g is described here. for details of the other bits, see the sections on the relevant modules. bit 3: timer g module standby mode control (tgckstp) bit 3 controls setting and clearing of module standby mode for timer g. tgckstp description 0 timer g is set to module standby mode 1 timer g module standby mode is cleared (initial value) 221 9.5.3 noise canceler the noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. the noise canceler is set by ncs* in pmr3. figure 9.8 shows a block diagram of the noise canceler. c dq latch c dq latch c dq latch c dq latch c dq latch match detector noise canceler output sampling clock input capture input signal sampling clock ? t ? t: set by cks1 and cks0 figure 9.8 noise canceler block diagram the noise canceler consists of five latch circuits connected in series and a match detector circuit. when the noise cancellation function is not used (ncs = 0), the system clock is selected as the sampling clock when the noise cancellation function is used (ncs = 1), the sampling clock is the internal clock selected by cks1 and cks0 in tmg, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match. if all the outputs do not match, the previous value is retained. after a reset, the noise canceler output is initialized when the falling edge of the input capture input signal has been sampled five times. therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. even if noise cancellation is not used, an input capture input signal pulse width of at least 2 or 2 sub is necessary to ensure that input capture operations are performed properly note: * an input capture signal may be generated when the ncs bit is modified. 222 figure 9.9 shows an example of noise canceler timing. in this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise. input capture input signal sampling clock noise canceler output eliminated as noise figure 9.9 noise canceler timing (example) 223 9.5.4 operation timer g is an 8-bit timer with built-in input capture and interval functions. 1. timer g functions timer g is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. the operation of these two functions is described below. a. input capture timer operation when the tmig bit is set to 1 in port mode register 1 (pmr1), timer g functions as an input capture timer*. in a reset, timer mode register g (tmg), timer counter g (tcg), input capture register gf (icrgf), and input capture register gr (icrgr) are all initialized to h 00. following a reset, tcg starts incrementing on the /64 internal clock. the input clock can be selected from four internal clock sources by bits cks1 and cks0 in tmg. when a rising edge/falling edge is detected in the input capture signal input from the tmig pin, the tcg value at that time is transferred to icrgr/icrgf. when the edge selected by iiegs in tmg is input, irrtg is set to 1 in irr2, and if the ientg bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. for details of the interrupt, see 3.3., interrupts. tcg can be cleared by a rising edge, falling edge, or both edges of the input capture signal, according to the setting of bits cclr1 and cclr0 in tmg. if tcg overflows when the input capture signal is high, the ovfh bit is set in tmg; if tcg overflows when the input capture signal is low, the ovfl bit is set in tmg. if the ovie bit in tmg is 1 when these bits are set, irrtg is set to 1 in irr2, and if the ientg bit in ienr2 is 1, timer g sends an interrupt request to the cpu. for details of the interrupt, see 3.3., interrupts. timer g has a built-in noise canceler that enables high-frequency component noise to be eliminated from pulses input from the tmig pin. for details, see 9.5.3, noise canceler. note: * an input capture signal may be generated when tmig is modified. b. interval timer operation when the tmig bit is cleared to 0 in pmr1, timer g functions as an interval timer. following a reset, tcg starts incrementing on the /64 internal clock. the input clock can be selected from four internal clock sources by bits cks1 and cks0 in tmg. tcg increments on the selected clock, and when it overflows from h ff to h 00, the ovfl bit is set to 1 in tmg. if the ovie bit in tmg is 1 at this time, irrtg is set to 1 in irr2, and if the ientg bit in ienr2 is 1, timer g sends an interrupt request to the cpu. for details of the interrupt, see 3.3., interrupts. 224 2. increment timing tcg is incremented by internal clock input. bits cks1 and cks0 in tmg select one of four internal clock sources ( /64, /32, /2, or w/4) created by dividing the system clock ( ) or watch clock ( w). 3. input capture input timing a. without noise cancellation function for input capture input, dedicated input capture functions are provided for rising and falling edges. figure 9.10 shows the timing for rising/falling edge input capture input. input capture input signal input capture signal f input capture signal r figure 9.10 input capture input timing (without noise cancellation function) b. with noise cancellation function when noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceler results in a delay of five sampling clock cycles from the input capture input signal edge. figure 9.11 shows the timing in this case. 225 input capture input signal sampling clock noise canceler output input capture signal r figure 9.11 input capture input timing (with noise cancellation function) 4. timing of input capture by input capture input figure 9.12 shows the timing of input capture by input capture input input capture signal tcg n-1 n n h'xx n+1 input capture register figure 9.12 timing of input capture by input capture input 226 5. tgc clear timing tcg can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. figure 9.13 shows the timing for clearing by both edges. i nput capture i nput signal i nput capture s ignal f i nput capture s ignal r t cg n n h'00 h'00 figure 9.13 tcg clear timing 227 6. timer g operation modes timer g operation modes are shown in table 9.13. table 9.13 timer g operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby tcg input capture reset functions * functions * functions/ halted * functions/ halted * functions/ halted * halted halted interval reset functions * functions * functions/ halted * functions/ halted * functions/ halted * halted halted icrgf reset functions * functions * functions/ halted * functions/ halted * functions/ halted * held held icrgr reset functions * functions * functions halted * functions/ halted * functions/ halted * held held tmg reset functions held held functions held held held note: * when w/4 is selected as the tcg internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when w/4 is selected as the tcg internal clock in watch mode, tcg and the noise canceler operate on the w/4 internal clock without regard to the sub subclock ( w/8, w/4, w/2). note that when another internal clock is selected, tcg and the noise canceler do not operate, and input of the input capture input signal does not result in input capture. to be operated timer g in subactive mode or subsleep mode, select w/4 for internal clock of tcg and also select w/2 for sub clock sub . when another internal clock is selected and when another sub clock ( w/8, w/4) is selected, tcg and noise canceler do not operate. 9.5.5 application notes 1. internal clock switching and tcg operation depending on the timing, tcg may be incremented by a switch between difference internal clock sources. table 9.14 shows the relation between internal clock switchover timing (by write to bits cks1 and cks0) and tcg operation. when tcg is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock ( ) or subclock ( w). for this reason, in a case like no. 3 in table 9.14 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing tcg to increment. 228 table 9.14 internal clock switching and tcg operation no. clock levels before and after modifying bits cks1 and cks0 tcg operation 1 goes from low level to low level clock before switching clock after switching count clock tcg n n+1 write to cks1 and cks0 2 goes from low level to high level clock before switching clock before switching count clock tcg n n+1 n+2 write to cks1 and cks0 3 goes from high level to low level * tcg n n+1 n+2 clock before switching clock before switching count clock write to cks1 and cks0 229 table 9.14 internal clock switching and tcg operation (cont) no. clock levels before and after modifying bits cks1 and cks0 tcg operation 4 goes from high level to high level tcg n n+1 n+2 clock before switching clock before switching count clock write to cks1 and cks0 note: * the switchover is seen as a falling edge, and tcg is incremented. 2. notes on port mode register modification the following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function. switching input capture input pin function note that when the pin function is switched by modifying tmig in port mode register 1 (pmr1), which performs input capture input pin control, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.15. 230 table 9.15 input capture input signal input edges due to input capture input pin switching, and conditions for their occurrence input capture input signal input edge conditions generation of rising edge when tmig is modified from 0 to 1 while the tmig pin is high when ncs is modified from 0 to 1 while the tmig pin is high, then tmig is modified from 0 to 1 before the signal is sampled five times by the noise canceler generation of falling edge when tmig is modified from 1 to 0 while the tmig pin is high when ncs is modified from 0 to 1 while the tmig pin is low, then tmig is modified from 0 to 1 before the signal is sampled five times by the noise canceler when ncs is modified from 0 to 1 while the tmig pin is high, then tmig is modified from 1 to 0 after the signal is sampled five times by the noise canceler note: when the p1 3 pin is not set as an input capture input pin, the timer g input capture input signal is low. switching input capture input noise canceler function when performing noise canceler function switching by modifying ncs in port mode register 3 (pmr3), which controls the input capture input noise canceler, tmig should first be cleared to 0. note that if ncs is modified without first clearing tmig, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.16. table 9.16 input capture input signal input edges due to noise canceler function switching, and conditions for their occurrence input capture input signal input edge conditions generation of rising edge when the tmig pin level is switched from low to high while tmig is set to 1, then ncs is modified from 0 to 1 before the signal is sampled five times by the noise canceler generation of falling edge when the tmig pin level is switched from high to low while tmig is set to 1, then ncs is modified from 1 to 0 before the signal is sampled five times by the noise canceler 231 when the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (iiegs) bit, the interrupt request flag will be set to 1. the interrupt request flag should therefore be cleared to 0 before use. figure 9.14 shows the procedure for port mode register manipulation and interrupt request flag clearing. when switching the pin function, set the interrupt-disabled state before manipulating the port mode register, then, after the port mode register operation has been performed, wait for the time required to confirm the input capture input signal as an input capture signal (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), before clearing the interrupt enable flag to 0. there are two ways of preventing interrupt request flag setting when the pin function is switched: by controlling the pin level so that the conditions shown in tables 9.15 and 9.16 are not satisfied, or by setting the opposite of the generated edge in the iiegs bit in tmg. set i bit to 1 in ccr manipulate port mode register tmig confirmation time clear interrupt request flag to 0 clear i bit to 0 in ccr disable interrupts. (interrupts can also be disabled by manipulating the interrupt enable bit in interrupt enable register 2.) after manipulating he port mode register, wait for the tmig confirmation time (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), then clear the interrupt enable flag to 0. enable interrupts figure 9.14 port mode register manipulation and interrupt enable flag clearing procedure 232 9.5.6 timer g application example using timer g, it is possible to measure the high and low widths of the input capture input signal as absolute values. for this purpose, cclr1 and cclr0 should both be set to 1 in tmg. figure 9.15 shows an example of the operation in this case. counter cleared tcg h'ff h'00 input capture input signal input capture register gf input capture register gr figure 9.15 timer g application example 233 9.6 watchdog timer 9.6.1 overview the watchdog timer has an 8-bit counter that is incremented by an input clock. if a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. features features of the watchdog timer are given below. ? /8192 or w/32). ? or 32/ w (from approximately 4 ms to 1000 ms when = 2.00 mhz). ? pss tcsrw tcw /8192 notation: tcsrw: tcw: pss: w/32 internal data bus reset signal timer control/status register w timer counter w prescaler s figure 9.16 block diagram of watchdog timer 234 3. register configuration table 9.17 shows the register configuration of the watchdog timer. table 9.17 watchdog timer registers name abbrev. r/w initial value address timer control/status register w tcsrw r/w h'aa h'ffb2 timer counter w tcw r/w h'00 h'ffb3 clock stop register 2 ckstp2 r/w h'ff h'fffb port mode register 3 pmr3 r/w h'00 h'ffca 9.6.2 register descriptions 1. timer control/status register w (tcsrw) bit initial value read/write 7 b6wi 1 r 6 tcwe 0 r/w 5 b4wi 1 r 4 tcsrwe 0 r/w 3 b2wi 1 r 0 wrst 0 r/w 2 wdon 0 r/w 1 b0wi 1 r * note: * ** * write is permitted only under certain conditions, which are given in the descriptions of the individual bits. tcsrw is an 8-bit read/write register that controls write access to tcw and tcsrw itself, controls watchdog timer operations, and indicates operating status. bit 7: bit 6 write inhibit (b6wi) bit 7 controls the writing of data to bit 6 in tcsrw. bit 7 b6wi description 0 bit 6 is write-enabled 1 bit 6 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. 235 bit 6: timer counter w write enable (tcwe) bit 6 controls the writing of data to tcw. bit 6 tcwe description 0 data cannot be written to tcw (initial value) 1 data can be written to tcw bit 5: bit 4 write inhibit (b4wi) bit 5 controls the writing of data to bit 4 in tcsrw. bit 5 b4wi description 0 bit 4 is write-enabled 1 bit 4 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit 4: timer control/status register w write enable (tcsrwe) bit 4 controls the writing of data to tcsrw bits 2 and 0. bit 4 tcsrwe description 0 data cannot be written to bits 2 and 0 (initial value) 1 data can be written to bits 2 and 0 bit 3: bit 2 write inhibit (b2wi) bit 3 controls the writing of data to bit 2 in tcsrw. bit 3 b2wi description 0 bit 2 is write-enabled 1 bit 2 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. 236 bit 2: watchdog timer on (wdon) bit 2 enables watchdog timer operation. bit 2 wdon description 0 watchdog timer operation is disabled (initial value) clearing conditions: reset, or when tcsrwe = 1 and 0 is written in both b2wi and wdon 1 watchdog timer operation is enabled setting conditions: when tcsrwe = 1 and 0 is written in b2wi and 1 is written in wdon counting starts when this bit is set to 1, and stops when this bit is cleared to 0. bit 1: bit 0 write inhibit (b0wi) bit 1 controls the writing of data to bit 0 in tcsrw. bit 1 b0wi description 0 bit 0 is write-enabled 1 bit 0 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit 0: watchdog timer reset (wrst) bit 0 indicates that tcw has overflowed, generating an internal reset signal. the internal reset signal generated by the overflow resets the entire chip. wrst is cleared to 0 by a reset from the res bit 0 wrst description 0 clearing conditions: reset by res pin when tcsrwe = 1, and 0 is written in both b0wi and wrst 1 setting conditions: when tcw overflows and an internal reset signal is generated 237 2. timer counter w (tcw) bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 4 tcw4 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w tcw is an 8-bit read/write up-counter, which is incremented by internal clock input. the input clock is /8192 or w/32. the tcw value can always be written or read by the cpu. when tcw overflows from h'ff to h'00, an internal reset signal is generated and wrst is set to 1 in tcsrw. upon reset, tcw is initialized to h'00. 3. clock stop register 2 (ckstpr2) wdckstp pwckstp ldckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the watchdog timer is described here. for details of the other bits, see the sections on the relevant modules. bit 2: watchdog timer module standby mode control (wdckstp) bit 2 controls setting and clearing of module standby mode for the watchdog timer. wdckstp description 0 watchdog timer is set to module standby mode 1 watchdog timer module standby mode is cleared (initial value) note: wdckstp is valid when the wdon bit is cleared to 0 in timer control/status register w (tcsrw). if wdckstp is set to 0 while wdon is set to 1 (during watchdog timer operation), 0 will be set in wdckstp but the watchdog timer will continue its watchdog function and will not enter module standby mode. when the watchdog function ends and wdon is cleared to 0 by software, the wdckstp setting will become valid and the watchdog timer will enter module standby mode. 238 4. port mode register 3 (pmr3) pmr3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins. only the bit relating to the watchdog timer is described here. for details of the other bits, see section 8, i/o ports. bit 5: watchdog timer source clock select (wdcks) wdcks description 0 /8192 selected (initial value) 1 w/32 selected 9.6.3 timer operation the watchdog timer has an 8-bit counter (tcw) that is incremented by clock input ( /8192 or w/32). the input clock is selected by bit wdcks in port mode register 3 (pmr3): /8192 is selected when wdcks is cleared to 0, and w/32 when set to 1. when tcsrwe = 1 in tcsrw, if 0 is written in b2wi and 1 is simultaneously written in wdon, tcw starts counting up. when the tcw count reaches h'ff, the next clock input causes the watchdog timer to overflow, and an internal reset signal is generated one reference clock ( or sub ) cycle later. the internal reset signal is output for 512 clock cycles of the osc clock. it is possible to write to tcw, causing tcw to count up from the written value. the overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in tcw. figure 9.17 shows an example of watchdog timer operations. example: = 2 mhz and the desired overflow period is 30 ms. 2 3 = 7.3 8192 the value set in tcw should therefore be 256 8 = 248 (h'f8). 239 h'f8 tcw overflow start h'f8 written in tcw h'f8 written in tcw reset internal reset signal 512 osc clock cycles h'ff h'00 tcw count value figure 9.17 typical watchdog timer operations (example) 9.6.4 watchdog timer operation states table 9.18 summarizes the watchdog timer operation states. table 9.18 watchdog timer operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tcw reset functions functions halted functions/ halted * halted halted halted tcsrw reset functions functions retained functions/ halted * retained retained retained note: * functions when w/32 is selected as the input clock. 240 9.7 asynchronous event counter (aec) 9.7.1 overview the asynchronous event counter is incremented by external event clock input. 1. features features of the asynchronous event counter are given below. can count asynchronous events can count external events input asynchronously without regard to the operation of base clocks and sub . the counter has a 16-bit configuration, enabling it to count up to 65536 (2 16 ) events. ? ? ? ? 241 2. block diagram figure 9.18 shows a block diagram of the asynchronous event counter. eccsr ech ecl irrec internal data bus ovl ovh ck ck aevl aevh : event counter control/status register : event counter h : event counter l : asynchronous event input h : asynchronous event input l : event counter overflow interrupt request flag notation: eccsr ech ecl aevh aevl irrec figure 9.18 block diagram of asynchronous event counter 242 3. pin configuration table 9.19 shows the asynchronous event counter pin configuration. table 9.19 pin configuration name abbrev. i/o function asynchronous event input h aevh input event input pin for input to event counter h asynchronous event input l aevl input event input pin for input to event counter l 4. register configuration table 9.20 shows the register configuration of the asynchronous event counter. table 9.20 asynchronous event counter registers name abbrev. r/w initial value address event counter control/status register eccsr r/w h'00 h'ff95 event counter h ech r h'00 h'ff96 event counter l ecl r h'00 h'ff97 clock stop register 2 ckstp2 r/w h'ff h'fffb 9.7.2 register descriptions 1. event counter control/status register (eccsr) ovh cuel crch crcl ovl ch2 cueh 76543210 0 0000000 r/w * r/w r/w r/w r/w * r/w r/w r/w bit note: * bits 7 and 6 can only be written with 0, for flag clearing. initial value read/write eccsr is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function. eccsr is initialized to h'00 upon reset. 243 bit 7: counter overflow flag h (ovh) bit 7 is a status flag indicating that ech has overflowed from h'ff to h'00. this flag is set when ech overflows. it is cleared by software but cannot be set by software. ovh is cleared by reading it when set to 1, then writing 0. when ech and ecl are used as a 16-bit event counter with ch2 cleared to 0, ovh functions as a status flag indicating that the 16-bit event counter has overflowed from h'ffff to h'0000. bit 7 ovh description 0 ech has not overflowed (initial value) clearing conditions: after reading ovh = 1, cleared by writing 0 to ovh 1 ech has overflowed setting conditions: set when ech overflows from h ff to h 00 bit 6: counter overflow flag l (ovl) bit 6 is a status flag indicating that ecl has overflowed from h'ff to h'00. this flag is set when ecl overflows. it is cleared by software but cannot be set by software. ovl is cleared by reading it when set to 1, then writing 0. bit 6 ovl description 0 ecl has not overflowed (initial value) clearing conditions: after reading ovl = 1, cleared by writing 0 to ovl 1 ecl has overflowed setting conditions: set when ecl overflows from h'ff to h'00 while ch2 is set to 1 bit 5: reserved bit bit 5 is reserved; it can be read and written, and is initialized to 0 upon reset. 244 bit 4: channel select (ch2) bit 4 selects whether ech and ecl are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels. when ch2 is cleared to 0, ech and ecl function as a 16-bit event counter which is incremented each time an event clock is input to the aevl pin as asynchronous event input. in this case, the overflow signal from ecl is selected as the ech input clock. when ch2 is set to 1, ech and ecl function as independent 8-bit event counters which are incremented each time an event clock is input to the aevh or aevl pin, respectively, as asynchronous event input. bit 4 ch2 description 0 ech and ecl are used together as a single-channel 16-bit event counter (initial value) 1 ech and ecl are used as two independent 8-bit event counter channels bit 3: count-up enable h (cueh) bit 3 enables event clock input to ech. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ech value is held. the aevh pin or the ecl overflow signal can be selected as the event clock source by bit ch2. bit 3 cueh description 0 ech event clock input is disabled (initial value) ech value is held 1 ech event clock input is enabled bit 2: count-up enable l (cuel) bit 3 enables event clock input to ecl. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ecl value is held. bit 2 cuel description 0 ecl event clock input is disabled (initial value) ecl value is held 1 ecl event clock input is enabled 245 bit 1: counter reset control h (crch) bit 1 controls resetting of ech. when this bit is cleared to 0, ech is reset. when 1 is written to this bit, the counter reset is cleared and the ech count-up function is enabled. bit 1 crch description 0 ech is reset (initial value) 1 ech reset is cleared and count-up function is enabled bit 0: counter reset control l (crcl) bit 0 controls resetting of ecl. when this bit is cleared to 0, ecl is reset. when 1 is written to this bit, the counter reset is cleared and the ecl count-up function is enabled. bit 0 crcl description 0 ecl is reset (initial value) 1 ecl reset is cleared and count-up function is enabled 2. event counter h (ech) ech7 ech2 ech1 ech0 ech6 ech5 ech4 ech3 76543210 0 0000000 r rrr rrr r bit initial value read/write ech is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ecl. either the external asynchronous event aevh pin or the overflow signal from lower 8-bit counter ecl can be selected as the input clock source by bit ch2. ech can be cleared to h'00 by software, and is also initialized to h'00 upon reset. 246 3. event counter l (ecl) ecl is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ech. the event clock from the external asynchronous event aevl pin is used as the input clock source. ecl can be cleared to h'00 by software, and is also initialized to h'00 upon reset. ecl7 ecl2 ecl1 ecl0 ecl6 ecl5 ecl4 ecl3 76543210 0 0000000 r rrr rrr r bit initial value read/write 4. clock stop register 2 (ckstpr2) wdckstp pwckstp ldckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the asynchronous event counter is described here. for details of the other bits, see the sections on the relevant modules. bit 3: asynchronous event counter module standby mode control (aeckstp) bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. aeckstp description 0 asynchronous event counter is set to module standby mode 1 asynchronous event counter module standby mode is cleared (initial value) 247 9.7.3 operation 1. 16-bit event counter operation when bit ch2 is cleared to 0 in eccsr, ech and ecl operate as a 16-bit event counter. figure 9.19 shows an example of the software processing when ech and ecl are used as a 16-bit event counter. start end clear ch2 to 0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 figure 9.19 example of software processing when using ech and ecl as 16-bit event counter as ch2 is cleared to 0 by a reset, ech and ecl operate as a 16-bit event counter after a reset. they can also be used as a 16-bit event counter by carrying out the software processing shown in the example in figure 9.19. the operating clock source is asynchronous event input from the aevl pin. when the next clock is input after the count value reaches h'ff in both ech and ecl, ech and ecl overflow from h'ffff to h'0000, the ovh flag is set to 1 in eccsr, the ech and ecl count values each return to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. 2. 8-bit event counter operation when bit ch2 is set to 1 in eccsr, ech and ecl operate as independent 8-bit event counters. figure 9.20 shows an example of the software processing when ech and ecl are used as 8-bit event counters. 248 start end set ch2 to 1 clear cueh, cuel, crch, and crcl to 0 clear ovh to 0 set cueh, cuel, crch, and crcl to 1 figure 9.20 example of software processing when using ech and ecl as 8-bit event counters ech and ecl can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.20. the 8-bit event counter operating clock source is asynchronous event input from the aevh pin for ech, and asynchronous event input from the aevl pin for ecl. when the next clock is input after the ech count value reaches h'ff, ech overflows, the ovh flag is set to 1 in eccsr, the ech count value returns to h'00, and counting up is restarted. similarly, when the next clock is input after the ecl count value reaches h'ff, ecl overflows, the ovl flag is set to 1 in eccsr, the ecl count value returns to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. 9.7.4 asynchronous event counter operation modes asynchronous event counter operation modes are shown in table 9.21. table 9.21 asynchronous event counter operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby eccsr reset functions functions held * functions functions held * held ech reset functions functions * functions * functions functions functions * halted ecl reset functions functions * functions * functions functions functions * halted note: * when an asynchronous external event is input, the counter increments but the counter overflow h/l flags are not affected. 249 9.7.5 application notes 1. when reading the values in ech and ecl, first clear bits cueh and cuel to 0 in eccsr to prevent asynchronous event input to the counter. the correct value will not be returned if the event counter increments while being read. when clear bits cueh and cuel to 0 in eccsr, ech and ecl sometimes count up. 2. use a clock with a frequency of up to 6 mhz (internal step-down circuit not used: v cc = 4.5 to 5.5 v), up to 4 mhz (internal step-down circuit not used: v cc = 3.0 to 5.5 v), up to 3.2 mhz (internal step-down circuit not used: v cc = 2.7 to 5.5 v), up to 2 mhz (v cc = 2.2 to 5.5 v), up to 1 mhz (others) for input to the aevh and aevl pins, and ensure that the high and low widths of the clock are at least 83 ns. the duty cycle is immaterial. mode maximum aevh/aevl pin input clock frequency 16-bit mode internal step-down circuit 8-bit mode active (high-speed), sleep (high-speed) not used: v cc = 4.5 to 5.5 v/6 mhz v cc = 3.0 to 5.5 v/4 mhz v cc = 2.6 to 5.5 v/3.2 mhz v cc = 2.2 to 5.5 v/2 mhz other than above/1 mhz internal step-down circuit used: v cc = 2.2 to 5.5 v/2 mhz other than above/1 mhz 8-bit mode active (medium-speed), sleep (medium-speed) ( /16) ( /32) ( /64) f osc = 400 khz to 4 mhz ( /128) 2 f osc f osc 1/2 f osc 1/4 f osc 8-bit mode watch, subactive, subsleep, standby ( w/2) ( w/4) w = 32.768 khz or 38.4 khz ( w/8) 1000 khz 500 khz 250 khz 3. when aec uses with 16-bit mode, set cueh in eccsr to 1 first, set crch in eccsr to 1 second, or set both cueh and crch to 1 at same time before clock entry. while aec is operating on 16-bit mode, do not change cueh. otherwise, ech will be miscounted up. 250 251 section 10 serial communication interface 10.1 overview the h8/3864 series is provided with two serial communication interfaces, sci3-1 and sci3-2. these two scis have identical functions. in this manual, the generic term sci3 is used to refer to both scis. serial communication interface 3 (sci3) can carry out serial data communication in either asynchronous or synchronous mode. it is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. 10.1.1 features features of sci3 are listed below. ? choice of asynchronous or synchronous mode for serial data communication ? asynchronous mode serial data communication is performed asynchronously, with synchronization provided character by character. in this mode, serial data can be exchanged with standard asynchronous communication lsis such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a multiprocessor communication function is also provided, enabling serial data communication among processors. there is a choice of 16 data transfer formats. data length 7, 8, 5 bits stop bit length 1 or 2 bits parity even, odd, or none multiprocessor bit ??or ? receive error detection parity, overrun, and framing errors break detection break detected by reading the rxd 3x pin level directly when a framing error occurs 252 ? synchronous mode serial data communication is synchronized with a clock. in his mode, serial data can be exchanged with another lsi that has a synchronous communication function. data length 8 bits receive error detection overrun errors ? full-duplex communication separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. the transmission and reception units are both double-buffered, allowing continuous transmission and reception. ? on-chip baud rate generator, allowing any desired bit rate to be selected ? choice of an internal or external clock as the transmit/receive clock source ? six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error 253 10.1.2 block diagram figure 10.1 shows a block diagram of sci3. clock txd rxd sck brr smr scr3 ssr tdr rdr tsr rsr spcr transmit/receive control circuit internal data bus notation: rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: spcr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter serial port control register interrupt request (tei, txi, rxi, eri) 3x internal clock ( /64, /16, w/2, ) external clock brc baud rate generator figure 10.1 sci3 block diagram 254 10.1.3 pin configuration table 10.1 shows the sci3 pin configuration. table 10.1 pin configuration name abbrev. i/o function sci3 clock sck 3x i/o sci3 clock input/output sci3 receive data input rxd 3x input sci3 receive data input sci3 transmit data output txd 3x output sci3 transmit data output 10.1.4 register configuration table 10.2 shows the sci3 register configuration. table 10.2 registers name abbrev. r/w initial value address serial mode register smr r/w h'00 h'ffa8/ff98 bit rate register brr r/w h'ff h'ffa9/ff99 serial control register 3 scr3 r/w h'00 h'ffaa/ff9a transmit data register tdr r/w h'ff h'ffab/ff9b serial data register ssr r/w h'84 h'ffac/ff9c receive data register rdr r h'00 h'ffad/ff9d transmit shift register tsr protected receive shift register rsr protected bit rate counter brc protected clock stop register 1 ckstpr1 r/w h'ff h'fffa serial port control register spcr r/w h'c0 h'ff91 255 10.2 register descriptions 10.2.1 receive shift register (rsr) bit read/write 7 6 5 4 3 0 2 1 rsr is a register used to receive serial data. serial data input to rsr from the rxd 3x pin is set in the order in which it is received, starting from the lsb (bit 0), and converted to parallel data. when one byte of data is received, it is transferred to rdr automatically. rsr cannot be read or written directly by the cpu. 10.2.2 receive data register (rdr) bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r rdr is an 8-bit register that stores received serial data. when reception of one byte of data is finished, the received data is transferred from rsr to rdr, and the receive operation is completed. rsr is then able to receive data. rsr and rdr are double-buffered, allowing consecutive receive operations. rdr is a read-only register, and cannot be written by the cpu. rdr is initialized to h'00 upon reset, and in standby, module standby or watch mode. 256 10.2.3 transmit shift register (tsr) b it r ead/write 7 6 5 4 3 0 2 1 tsr is a register used to transmit serial data. transmit data is first transferred from tdr to tsr, and serial data transmission is carried out by sending the data to the txd 3x pin in order, starting from the lsb (bit 0). when one byte of data is transmitted, the next byte of transmit data is transferred to tdr, and transmission started, automatically. data transfer from tdr to tsr is not performed if no data has been written to tdr (if bit tdre is set to 1 in the serial status register (ssr)). tsr cannot be read or written directly by the cpu. 10.2.4 transmit data register (tdr) b it i nitial value r ead/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w tdr is an 8-bit register that stores transmit data. when tsr is found to be empty, the transmit data written in tdr is transferred to tsr, and serial data transmission is started. continuous transmission is possible by writing the next transmit data to tdr during tsr serial data transmission. tdr can be read or written by the cpu at any time. tdr is initialized to h'ff upon reset, and in standby, module standby, or watch mode. 257 10.2.5 serial mode register (smr) bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 pm 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w smr is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. smr can be read or written by the cpu at any time. smr is initialized to h'00 upon reset, and in standby, module standby, or watch mode. bit 7: communication mode (com) bit 7 selects whether sci3 operates in asynchronous mode or synchronous mode. bit 7 com description 0 asynchronous mode (initial value) 1 synchronous mode bit 6: character length (chr) bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. in synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. bit 6 chr description 0 8-bit data/5-bit data * 2 (initial value) 1 7-bit data * 1 /5-bit data * 2 notes: 1. when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 2. when 5-bit data is selected, set both pe and mp to 1. the three most significant bits (bits 7, 6, and 5) of tdr are not transmitted. 258 bit 5: parity enable (pe) bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. in synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. bit 5 pe description 0 parity bit addition and checking disabled * 2 (initial value) 1 parity bit addition and checking enabled * 1/ * 2 notes: 1. when pe is set to 1, even or odd parity, as designated by bit pm, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit pm. 2. for the case where 5-bit data is selected, see table 10.11. bit 4: parity mode (pm) bit 4 selects whether even or odd parity is to be used for parity addition and checking. the pm bit setting is only valid in asynchronous mode when bit pe is set to 1, enabling parity bit addition and checking. the pm bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled. bit 4 pm description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. 2. when odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number. 259 bit 3: stop bit length (stop) bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. the stop bit setting is only valid in asynchronous mode. when synchronous mode is selected the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. in transmission, two 1 bits (stop bits) are added at the end of a transmit character. in reception, only the first of the received stop bits is checked, irrespective of the stop bit setting. if the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. bit 2: multiprocessor mode (mp) bit 2 enables or disables the multiprocessor communication function. when the multiprocessor communication function is disabled, the parity settings in the pe and pm bits are invalid. the mp bit setting is only valid in asynchronous mode. when synchronous mode is selected the mp bit should be set to 0. for details on the multiprocessor communication function, see 10.1.6, multiprocessor communication function. bit 2 mp description 0 multiprocessor communication function disabled * (initial value) 1 multiprocessor communication function enabled * note: * for the case where 5-bit data is selected, see table 10.11. 260 bits 1 and 0: clock select 1, 0 (cks1, cks0) bits 1 and 0 choose ?64, ?16, ?/2, or ?as the clock source for the baud rate generator. for the relation between the clock source, bit rate register setting, and baud rate, see 8, bit rate register (brr). bit 1 cks1 bit 0 cks0 description 00 clock (initial value) 01 w/2 clock * 1 / w clock * 2 10 /16 clock 11 /64 clock notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode 3. in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. 10.2.6 serial control register 3 (scr3) b it i nitial value r ead/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w scr3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. scr3 can be read or written by the cpu at any time. scr3 is initialized to h'00 upon reset, and in standby, module standby or watch mode. 261 bit 7: transmit interrupt enable (tie) bit 7 selects enabling or disabling of the transmit data empty interrupt request (txi) when transmit data is transferred from the transmit data register (tdr) to the transmit shift register (tsr), and bit tdre in the serial status register (ssr) is set to 1. txi can be released by clearing bit tdre or bit tie to 0. bit 7 tie description 0 transmit data empty interrupt request (txi) disabled (initial value) 1 transmit data empty interrupt request (txi) enabled bit 6: receive interrupt enable (rie) bit 6 selects enabling or disabling of the receive data full interrupt request (rxi) and the receive error interrupt request (eri) when receive data is transferred from the receive shift register (rsr) to the receive data register (rdr), and bit rdrf in the serial status register (ssr) is set to 1. there are three kinds of receive error: overrun, framing, and parity. rxi can be released by clearing bit rdrf or the fer, per, or oer error flag to 0, or by clearing bit rie to 0. bit 6 rie description 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled (initial value) 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled bit 5: transmit enable (te) bit 5 selects enabling or disabling of the start of transmit operation. bit 5 te description 0 transmit operation disabled * 1 (txd pin is i/o port) (initial value) 1 transmit operation enabled * 2 (txd pin is transmit data pin) notes: 1. bit tdre in ssr is fixed at 1. 2. when transmit data is written to tdr in this state, bit tdr in ssr is cleared to 0 and serial data transmission is started. be sure to carry out serial mode register (smr) settings, and setting of bit spc31 or spc32 in spcr, to decide the transmission format before setting bit te to 1. 262 bit 4: receive enable (re) bit 4 selects enabling or disabling of the start of receive operation. bit 4 re description 0 receive operation disabled * 1 (rxd pin is i/o port) (initial value) 1 receive operation enabled * 2 (rxd pin is receive data pin) notes: 1. note that the rdrf, fer, per, and oer flags in ssr are not affected when bit re is cleared to 0, and retain their previous state. 2. in this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. be sure to carry out serial mode register (smr) settings to decide the reception format before setting bit re to 1. bit 3: multiprocessor interrupt enable (mpie) bit 3 selects enabling or disabling of the multiprocessor interrupt request. the mpie bit setting is only valid when asynchronous mode is selected and reception is carried out with bit mp in smr set to 1. the mpie bit setting is invalid when bit com is set to 1 or bit mp is cleared to 0. bit 3 mpie description 0 multiprocessor interrupt request disabled (normal receive operation) (initial value) clearing conditions: when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled * note: * receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and oer status flags in ssr is not performed. rxi, eri, and setting of the rdrf, fer, and oer flags in ssr, are disabled until data with the multiprocessor bit set to 1 is received. when a receive character with the multiprocessor bit set to 1 is received, bit mpbr in ssr is set to 1, bit mpie is automatically cleared to 0, and rxi and eri requests (when bits tie and rie in serial control register 3 (scr3) are set to 1) and setting of the rdrf, fer, and oer flags are enabled. 263 bit 2: transmit end interrupt enable (teie) bit 2 selects enabling or disabling of the transmit end interrupt request (tei) if there is no valid transmit data in tdr when msb data is to be sent. bit 2 teie description 0 transmit end interrupt request (tei) disabled (initial value) 1 transmit end interrupt request (tei) enabled * note: * tei can be released by clearing bit tdre to 0 and clearing bit tend to 0 in ssr, or by clearing bit teie to 0. bits 1 and 0: clock enable 1 and 0 (cke1, cke0) bits 1 and 0 select the clock source and enabling or disabling of clock output from the sck 3x pin. the combination of cke1 and cke0 determines whether the sck 3x pin functions as an i/o port, a clock output pin, or a clock input pin. the cke0 bit setting is only valid in case of internal clock operation (cke1 = 0) in asynchronous mode. in synchronous mode, or when external clock operation is used (cke1 = 1), bit cke0 should be cleared to 0. after setting bits cke1 and cke0, set the operating mode in the serial mode register (smr). for details on clock source selection, see table 10.4 in 10.1.3, operation. bit 1 bit 0 description cke1 cke0 communication mode clock source sck 3x pin function 0 0 asynchronous internal clock i/o port * 1 synchronous internal clock serial clock output * 1 0 1 asynchronous internal clock clock output * 2 synchronous reserved 1 0 asynchronous external clock clock input * 3 synchronous external clock serial clock input 1 1 asynchronous reserved synchronous reserved notes: 1. initial value 2. a clock with the same frequency as the bit rate is output. 3. input a clock with a frequency 16 times the bit rate. 264 10.2.7 serial status register (ssr) b it i nitial value r ead/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 oer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r ***** note: * only a write of 0 for flag clearing is possible. ssr is an 8-bit register containing status flags that indicate the operational status of sci3, and multiprocessor bits. ssr can be read or written by the cpu at any time, but only a write of 1 is possible to bits tdre, rdrf, oer, per, and fer. in order to clear these bits by writing 0, 1 must first be read. bits tend and mpbr are read-only bits, and cannot be modified. ssr is initialized to h'84 upon reset, and in standby, module standby, or watch mode. bit 7: transmit data register empty (tdre) bit 7 indicates that transmit data has been transferred from tdr to tsr. bit 7 tdre description 0 transmit data written in tdr has not been transferred to tsr clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmit data has not been written to tdr, or transmit data written in tdr has been transferred to tsr setting conditions: when bit te in scr3 is cleared to 0 when data is transferred from tdr to tsr (initial value) 265 bit 6: receive data register full (rdrf) bit 6 indicates that received data is stored in rdr. bit 6 rdrf description 0 there is no receive data in rdr (initial value) clearing conditions: after reading rdrf = 1, cleared by writing 0 to rdrf when rdr data is read by an instruction 1 there is receive data in rdr setting conditions: when reception ends normally and receive data is transferred from rsr to rdr note: if an error is detected in the receive data, or if the re bit in scr3 has been cleared to 0, rdr and bit rdrf are not affected and retain their previous state. note that if data reception is completed while bit rdrf is still set to 1, an overrun error (oer) will result and the receive data will be lost. bit 5: overrun error (oer) bit 5 indicates that an overrun error has occurred during reception. bit 5 oer description 0 reception in progress or completed * 1 (initial value) clearing conditions: after reading oer = 1, cleared by writing 0 to oer 1 an overrun error has occurred during reception * 2 setting conditions: when reception is completed with rdrf set to 1 notes: 1. when bit re in scr3 is cleared to 0, bit oer is not affected and retains its previous state. 2. rdr retains the receive data it held before the overrun error occurred, and data received after the error is lost. reception cannot be continued with bit oer set to 1, and in synchronous mode, transmission cannot be continued either. 266 bit 4: framing error (fer) bit 4 indicates that a framing error has occurred during reception in asynchronous mode. bit 4 fer description 0 reception in progress or completed * 1 (initial value) clearing conditions: after reading fer = 1, cleared by writing 0 to fer 1 a framing error has occurred during reception setting conditions: when the stop bit at the end of the receive data is checked for a value of 1 at the end of reception, and the stop bit is 0 * 2 notes: 1. when bit re in scr3 is cleared to 0, bit fer is not affected and retains its previous state. 2. note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. when a framing error occurs the receive data is transferred to rdr but bit rdrf is not set. reception cannot be continued with bit fer set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1. bit 3: parity error (per) bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. bit 3 per description 0 reception in progress or completed * 1 (initial value) clearing conditions: after reading per = 1, cleared by writing 0 to per 1 a parity error has occurred during reception * 2 setting conditions: when the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit pm in the serial mode register (smr) notes: 1. when bit re in scr3 is cleared to 0, bit per is not affected and retains its previous state. 2. receive data in which it a parity error has occurred is still transferred to rdr, but bit rdrf is not set. reception cannot be continued with bit per set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1. 267 bit 2: transmit end (tend) bit 2 indicates that bit tdre is set to 1 when the last bit of a transmit character is sent. bit 2 is a read-only bit and cannot be modified. bit 2 tend description 0 transmission in progress clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmission ended (initial value) setting conditions: when bit te in scr3 is cleared to 0 when bit tdre is set to 1 when the last bit of a transmit character is sent bit 1: multiprocessor bit receive (mpbr) bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. bit 1 is a read-only bit and cannot be modified. bit 1 mpbr description 0 data in which the multiprocessor bit is 0 has been received * (initial value) 1 data in which the multiprocessor bit is 1 has been received note: * when bit re is cleared to 0 in scr3 with the multiprocessor format, bit mpbr is not affected and retains its previous state. bit 0: multiprocessor bit transfer (mpbt) bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous mode. the bit mpbt setting is invalid when synchronous mode is selected, when the multiprocessor communication function is disabled, and when not transmitting. bit 0 mpbt description 0 a 0 multiprocessor bit is transmitted (initial value) 1 a 1 multiprocessor bit is transmitted 268 10.2.8 bit rate register (brr) b it i nitial value r ead/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w brr is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 of the serial mode register (smr). brr can be read or written by the cpu at any time. brr is initialized to h'ff upon reset, and in standby, module standby, or watch mode. table 10.3 shows examples of brr settings in asynchronous mode. the values shown are for active (high-speed) mode. table 10.3 examples of brr settings for various bit rates (asynchronous mode) (1) osc 32.8 khz 38.4 khz 2 mhz 2.4576 mhz 4 mhz b bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) n n error (%) 110 cannot be used, 221 0.83 150 as error 0 3 0 2 12 0.16 3 3 0 2 25 0.16 200 exceeds 3% 0 2 0 0 155 0.16 3 2 0 250 0 124 0 0 153 0.26 0 249 0 300 0 1 0 0 103 0.16 3 1 0 2 12 0.16 600 0 0 0 0 51 0.16 3 0 0 0 103 0.16 1200 0 25 0.16 2 1 0 0 51 0.16 2400 0 12 0.16 2 0 0 0 25 0.16 4800 0 7 0 0 12 0.16 9600 030 19200 010 31250 010 38400 000 269 notes: 1. the setting should be made so that the error is not more than 1%. 2. the value set in brr is given by the following equation: n = osc 1 (64 osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.4.) 3. the error in table 10.3 is the value obtained from the following equation, rounded to two decimal places. error (%) = b (rate obtained from n, n, osc) r(bit rate in left-hand column in table 10.3.) table 10.4 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode 3. in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. table 10.5 shows the maximum bit rate for each frequency. the values shown are for active (high-speed) mode. 270 table 10.5 maximum bit rate for each frequency (asynchronous mode) maximum bit rate setting osc (mhz) (bit/s) n n 0.0384 * 600 0 0 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 * : when smr is set up to cks1 = 0 , cks0 = 1 . table 10.6 shows examples of brr settings in synchronous mode. the values shown are for active (high-speed) mode. table 10.6 examples of brr settings for various bit rates (synchronous mode) osc b bit rate 38.4 khz 2 mhz 4 mhz (bit/s) n n error n n error n n error 200 0 23 0 250 2 124 0 300 2 0 0 500 1k 0 249 0 2.5k 0 99 0 0 199 0 5k 04900990 10k 02400490 25k 0900190 50k 040090 100k 040 250k 000010 500k 0 0 0 1m blank: cannot be set. : a setting can be made, but an error will result. 271 notes: the value set in brr is given by the following equation: n = osc 1 (8 osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.7.) table 10.7 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode 3. in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. 272 10.2.9 clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bits relating to sci3 are described here. for details of the other bits, see the sections on the relevant modules. bit 6: sci3-1 module standby mode control (s31ckstp) bit 6 controls setting and clearing of module standby mode for sci31. s31ckstp description 0 sci3-1 is set to module standby mode 1 sci3-1 module standby mode is cleared (initial value) note: all sci31 register is initialized in module standby mode. bit 5: sci3-2 module standby mode control (s32ckstp) bit 5 controls setting and clearing of module standby mode for sci32. s32ckstp description 0 sci3-2 is set to module standby mode 1 sci3-2 module standby mode is cleared (initial value) note: all sci32 register is initialized in module standby mode. 273 10.2.10 serial port control register (spcr) bit initial value read/write 7 1 6 1 5 spc32 0 r/w 4 spc31 0 r/w 3 scinv3 0 r/w 0 scinv0 0 r/w 2 scinv2 0 r/w 1 scinv1 0 r/w spcr is an 8-bit readable/writable register that performs rxd 31 , rxd 32 , txd 31 , and txd 32 pin input/output data inversion switching. spcr is initialized to h'c0 by a reset. bit 0: rxd 31 pin input data inversion switch bit 0 specifies whether or not rxd 31 pin input data is to be inverted. bit 0 scinv0 description 0 rxd 31 input data is not inverted (initial value) 1 rxd 31 input data is inverted bit 1: txd 31 pin output data inversion switch bit 1 specifies whether or not txd 31 pin output data is to be inverted. bit 1 scinv1 description 0 txd 31 output data is not inverted (initial value) 1 txd 31 output data is inverted bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted. bit 2 scinv2 description 0 rxd 32 input data is not inverted (initial value) 1 rxd 32 input data is inverted 274 bit 3: txd 32 pin output data inversion switch bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0 txd 32 output data is not inverted (initial value) 1 txd 32 output data is inverted bit 4: p3 5 /txd 31 pin function switch (spc31) this bit selects whether pin p3 5 /txd 31 is used as p3 5 or as txd 31 . bit 4 spc31 description 0 functions as p3 5 i/o pin (initial value) 1 functions as txd 31 output pin * note: * set the te bit in scr3 after setting this bit to 1. bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. bits 7 to 6: reserved bits bits 7 to 6 are reserved; they are always read as 1 and cannot be modified. 275 10.3 operation 10.3.1 overview sci3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. the serial mode register (smr) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8. the clock source for sci3 is determined by bit com in smr and bits cke1 and cke0 in scr3, as shown in table 10.9. 1. synchronous mode ? ? ? ? ? ? ? 276 table 10.8 smr settings and corresponding data transfer formats smr data transfer format bit 7 com bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multiprocessor bit parity bit stop bit length 0 0 0 0 0 asynchronous 8-bit data no no 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 0 1 0 0 8-bit data yes no 1 bit 1 2 bits 1 0 5-bit data no 1 bit 1 2 bits 1 0 0 7-bit data yes 1 bit 1 2 bits 1 0 5-bit data no yes 1 bit 1 2 bits 1 * 0 ** synchronous mode 8-bit data no no no * : don t care 277 table 10.9 smr and scr3 settings and clock source selection smr scr3 bit 7 bit 1 bit 0 transmit/receive clock com cke1 cke0 mode clock source sck 3x pin function 0 0 0 asynchronous internal i/o port (sck 3x pin not used) 1 mode outputs clock with same frequency as bit rate 1 0 external outputs clock with frequency 16 times bit rate 1 0 0 synchronous internal outputs serial clock 1 0 mode external inputs serial clock 0 1 1 reserved (do not specify these combinations) 10 1 11 1 3. interrupts and continuous transmission/reception sci3 can carry out continuous reception using rxi and continuous transmission using txi. these interrupts are shown in table 10.10. table 10.10 transmit/receive interrupts interrupt flags interrupt request conditions notes rxi rdrf rie when serial reception is performed normally and receive data is transferred from rsr to rdr, bit rdrf is set to 1, and if bit rie is set to 1 at this time, rxi is enabled and an interrupt is requested. (see figure 10.2 (a).) the rxi interrupt routine reads the receive data transferred to rdr and clears bit rdrf to 0. continuous reception can be performed by repeating the above operations until reception of the next rsr data is completed. txi tdre tie when tsr is found to be empty (on completion of the previous transmission) and the transmit data placed in tdr is transferred to tsr, bit tdre is set to 1. if bit tie is set to 1 at this time, txi is enabled and an interrupt is requested. (see figure 10.2 (b).) the txi interrupt routine writes the next transmit data to tdr and clears bit tdre to 0. continuous transmission can be performed by repeating the above operations until the data transferred to tsr has been transmitted. tei tend teie when the last bit of the character in tsr is transmitted, if bit tdre is set to 1, bit tend is set to 1. if bit teie is set to 1 at this time, tei is enabled and an interrupt is requested. (see figure 10.2 (c).) tei indicates that the next transmit data has not been written to tdr when the last bit of the transmit character in tsr is sent. 278 rdr rsr (reception in progress) rdrf = 0 rxd 3x pin rdr rsr (reception completed, transfer) rdrf 1 (rxi request when rie = 1) rxd 3x pin figure 10.2 (a) rdrf setting and rxi interrupt tdr (next transmit data) tsr (transmission in progress) tdre = 0 t xd 3x pin tdr tsr (transmission completed, transfer) tdre 1 (txi request when tie = 1) txd 3x pin figure 10.2 (b) tdre setting and txi interrupt tdr tsr (transmission in progress) tend = 0 txd 3x pin tdr tsr (reception completed) tend 1 (tei request when teie = 1) txd 3x pin figure 10.2 (c) tend setting and tei interrupt 279 10.3.2 operation in asynchronous mode in asynchronous mode, serial communication is performed with synchronization provided character by character. a start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. sci3 has separate transmission and reception units, allowing full-duplex communication. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.3. serial data start bit 1 bit transmit/receive data parity bit stop bit(s) 5, 7 or 8 bits one transfer data unit (character or frame) 1 bit or none 1 or 2 bits mark state 1 (msb) (lsb) figure 10.3 data format in asynchronous communication in asynchronous communication, the communication line is normally in the mark state (high level). sci3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. one transfer data character consists of a start bit (low level), followed by transmit/receive data (lsb-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. the data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. 280 table 10.11 shows the 12 data transfer formats that can be set in asynchronous mode. the format is selected by the settings in the serial mode register (smr). 281 table 10.11 data transfer formats (asynchronous mode) 1 chr 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 pe mp stop 2 3 4 5 8-bit data serial data transfer format and frame length smr stop s 6 7 8 9 10 11 12 8-bit data s 7-bit data stop stop s stop 7-bit data s stop stop 5-bit data s stop 5-bit data s stop stop 8-bit data p s stop 8-bit data p s stop stop 8-bit data mpb s stop 8-bit data mpb s stop stop 7-bit data p stop s stop 7-bit data stop s 5-bit data stop p p p s 5-bit data stop stop s notation: s: stop: p: mpb: start bit stop bit parity bit multiprocessor bit stop 7-bit data stop s 7-bit data stop mpb mpb s 282 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 3x pin can be selected as the sci3 transmit/receive clock. the selection is made by means of bit com in smr and bits sce1 and cke0 in scr3. see table 10.9 for details on clock source selection. when an external clock is input at the sck 3x pin, the clock frequency should be 16 times the bit rate. when sci3 operates on an internal clock, the clock can be output at the sck 3x pin. in this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10.4. 1 character (1 frame) 0 d0d1d2d3d4d5d6d70/1 1 1 clock serial data figure 10.4 phase relationship between output clock and transfer data (asynchronous mode) (8-bit data, parity, 2 stop bits) 3. data transfer operations sci3 initialization before data is transferred on sci3, bits te and re in scr3 must first be cleared to 0, and then sci3 must be initialized as follows. note: if the operation mode or data transfer format is changed, bits te and re must first be cleared to 0. when bit te is cleared to 0, bit tdre is set to 1. note that the rdrf, per, fer, and oer flags and the contents of rdr are retained when re is cleared to 0. when an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. when an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization. 283 figure 10.5 shows an example of a flowchart for initializing sci3. start end clear bits te and re to 0 in scr3 1 2 3 set bits cke1 and cke0 set data transfer format in smr set bits spc31 and spc32 to 1 in spcr set value in brr no wait yes 4 set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in pmr7 has 1-bit period elapsed? set clock selection in scr3. be sure to clear the other bits to 0. if clock output is selected in asynchronous mode, the clock is output immediately after setting bits cke1 and cke0. if clock output is selected for reception in synchronous mode, the clock is output immediately after bits cke1, cke0, and re are set to 1. set the data transfer format in the serial mode register (smr). write the value corresponding to the transfer rate in brr. this operation is not necessary when an external clock is selected. wait for at least one bit period, then set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in pmr7. setting bits te and re enables the txd3x and rxd3x pins to be used. in asynchronous mode the mark state is established when transmitting, and the idle state waiting for a start bit when receiving. 1. 2. 3. 4. figure 10.5 example of sci3 initialization flowchart 284 transmitting figure 10.6 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 2 3 write transmit data to tdr read bit tend in ssr set pdr = 0, pcr = 1 clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? no yes yes yes no break output? read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. (after the te bit is set to 1, one frame of 1s is output, then transmission is possible.) when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.6 example of data transmission flowchart (asynchronous mode) 285 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd3x pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1, bit tend in ssr bit is set to 1the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.12 shows an example of the operation when transmitting in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.7 example of operation when transmitting in asynchronous mode (8-bit data, parity, 1 stop bit) 286 receiving figure 10.8 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bits oer, per, fer in ssr 1 2 3 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + per + fer = 1? no rdrf = 1? yes continue data reception? no no yes receive error processing (a) read bits oer, per, and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the stop bit of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. 1. 2. 3. figure 10.8 example of data reception flowchart (asynchronous mode) 287 start receive error processing end of receive error processing 4 clear bits oer, per, fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? yes per = 1? no no no no overrun error processing framing error processing (a) parity error processing if a receive error has occurred, read bits oer, per, and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer, per, and fer are all cleared to 0. reception cannot be resumed if any of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 3x pin. 4. figure 10.8 example of data reception flowchart (asynchronous mode) (cont) 288 sci3 operates as follows when receiving data. sci3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. reception is carried out in accordance with the relevant data transfer format in table 10.11. the received data is first placed in rsr in lsb-to-msb order, and then the parity bit and stop bit(s) are received. sci3 then carries out the following checks. ? ? ? table 10.12 receive error detection conditions and receive data processing receive error abbreviation detection conditions receive data processing overrun error oer when the next date receive operation is completed while bit rdrf is still set to 1 in ssr receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the parity (odd or even) set in smr is different from that of the received data receive data is transferred from rsr to rdr 289 figure 10.9 shows an example of the operation when receiving in asynchronous mode. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1 d0 d1 d7 0/1 1 0 1 0 d0 d1 d7 0/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 start bit detected eri request in response to framing error figure 10.9 example of operation when receiving in asynchronous mode (8-bit data, parity, 1 stop bit) 10.3.3 operation in synchronous mode in synchronous mode, sci3 transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. sci3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 290 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.10. serial clock serial data note: * high level except in continuous transmission/reception lsb msb * * bit 1 bit 0 bit 2 bit 3 bit 4 8 bits one transfer data unit (character or frame) bit 5 bit 6 bit 7 don't care don't care figure 10.10 data format in synchronous communication in synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. data confirmation is guaranteed at the rising edge of the serial clock. one transfer data character begins with the lsb and ends with the msb. after output of the msb, the communication line retains the msb state. when receiving in synchronous mode, sci3 latches receive data at the rising edge of the serial clock. the data transfer format uses a fixed 8-bit data length. parity and multiprocessor bits cannot be added. 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 3x pin can be selected as the sci3 serial clock. the selection is made by means of bit com in smr and bits cke1 and cke0 in scr3. see table 10.9 for details on clock source selection. when sci3 operates on an internal clock, the serial clock is output at the sck 3x pin. eight pulses of the serial clock are output in transmission or reception of one character, and when sci3 is not transmitting or receiving, the clock is fixed at the high level. 291 3. data transfer operations sci3 initialization data transfer on sci3 first of all requires that sci3 be initialized as described in 10.1.4 (3)(a). sci3 initialization, and shown in figure 10.5. transmitting figure 10.11 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 2 write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? yes yes no read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically, the clock is output, and data transmission is started. when clock output is selected, the clock is output and data transmission started when data is written to tdr. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. 1. 2. figure 10.11 example of data transmission flowchart (synchronous mode) 292 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. when clock output mode is selected, sci3 outputs 8 serial clock pulses. when an external clock is selected, data is output in synchronization with the input clock. serial data is transmitted from the txd3x pin in order from the lsb (bit 0) to the msb (bit 7). when the msb (bit 7) is sent, checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and starts transmission of the next frame. if bit tdre is set to 1, sci3 sets bit tend to 1 in ssr, and after sending the msb (bit 7), retains the msb state. if bit teie in scr3 is set to 1 at this time, a tei request is made. after transmission ends, the sck pin is fixed at the high level. note: transmission is not possible if an error flag (oer, fer, or per) that indicates the data reception status is set to 1. check that these error flags are all cleared to 0 before a transmit operation. figure 10.12 shows an example of the operation when transmitting in synchronous mode. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi request data written to tdr tdre cleared to 0 txi request tei request figure 10.12 example of operation when transmitting in synchronous mode 293 receiving figure 10.13 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bit oer in ssr 1 2 3 4 read bit rdrf in ssr overrun error processing 4 clear bit oer to 0 in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer = 1? no rdrf = 1? yes continue data reception? no no yes overrun error processing end of overrun error processing start overrun error processing read bit oer in the serial status register (ssr) to determine if there is an error. if an overrun error has occurred, execute overrun error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. reception cannot be resumed if bit oer is set to 1. 1. 2. 3. 4. figure 10.13 example of data reception flowchart (synchronous mode) 294 sci3 operates as follows when receiving data. sci3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. the received data is placed in rsr in lsb-to-msb order. after the data has been received, sci3 checks that bit rdrf is set to 0, indicating that the receive data can be transferred from rsr to rdr. if this check shows that there is no overrun error, bit rdrf is set to 1, and the receive data is stored in rdr. if bit rie is set to 1 in scr3, an rxi interrupt is requested. if the check identifies an overrun error, bit oer is set to 1. bit rdrf remains set to 1. if bit rie is set to 1 in scr3, an eri interrupt is requested. see table 10.12 for the conditions for detecting a receive error, and receive data processing. note: no further receive operations are possible while a receive error flag is set. bits oer, fer, per, and rdrf must therefore be cleared to 0 before resuming reception. figure 10.14 shows an example of the operation when receiving in synchronous mode. serial clock serial data bit 0 bit 7 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi request rdr data read rdre cleared to 0 rxi request eri request in response to overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 10.14 example of operation when receiving in synchronous mode 295 simultaneous transmit/receive figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. this procedure should be followed for simultaneous transmission/reception after initializing sci3. start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 2 3 4 write transmit data to tdr read bit oer in ssr read bit rdrf in ssr clear bits te and re to 0 in scr3 yes tdre = 1? no oer = 1? no rdrf = 1? yes continue data transmission/reception? no yes no read receive data in rdr yes overrun error processing read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data transmission/reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. before receiving the msb (bit 7) of the current frame, also read tdre = 1 to confirm that a write can be performed, then write data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically, and when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. transmis- sion and reception cannot be resumed if bit oer is set to 1. see figure 10-13 for details on overrun error processing. 1. 2. 3. 4. figure 10.15 example of simultaneous data transmission/reception flowchart (synchronous mode) 296 notes: 1. when switching from transmission to simultaneous transmission/reception, check that sci3 has finished transmitting and that bits tdre and tend are set to 1, clear bit te to 0, and then set bits te and re to 1 simultaneously. 2. when switching from reception to simultaneous transmission/reception, check that sci3 has finished receiving, clear bit re to 0, then check that bit rdrf and the error flags (oer, fer, and per) are cleared to 0, and finally set bits te and re to 1 simultaneously. 10.3.4 multiprocessor communication function the multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). in multiprocessor communication, each receiver is assigned its own id code. the serial communication cycle consists of two cycles, an id transmission cycle in which the receiver is specified, and a data transmission cycle in which the transfer data is sent to the specified receiver. these two cycles are differentiated by means of the multiprocessor bit, 1 indicating an id transmission cycle, and 0, a data transmission cycle. the sender first sends transfer data with a 1 multiprocessor bit added to the id code of the receiver it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the transmit data. when a receiver receives transfer data with the multiprocessor bit set to 1, it compares the id code with its own id code, and if they are the same, receives the transfer data sent next. if the id codes do not match, it skips the transfer data until data with the multiprocessor bit set to 1 is sent again. in this way, a number of processors can exchange data among themselves. figure 10.16 shows an example of communication between processors using the multiprocessor format. 297 sender serial data receiver a (id = 01) (id = 02) receiver b h'01 id transmission cycle (specifying the receiver) data transmission cycle (sending data to the receiver specified buy the id) mpb: multiprocessor bit (mpb = 1) (mpb = 0) h'aa communication line (id = 03) receiver c (id = 04) receiver d figure 10.16 example of inter-processor communication using multiprocessor format (sending data h'aa to receiver a) there is a choice of four data transfer formats. if a multiprocessor format is specified, the parity bit specification is invalid. see table 10.11 for details. for details on the clock used in multiprocessor communication, see 10.1.4, operation in synchronous mode. multiprocessor transmitting figure 10.17 shows an example of a flowchart for multiprocessor data transmission. this procedure should be followed for multiprocessor data transmission after initializing sci3. 298 start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 3 2 set bit mpdt in ssr write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 set pdr = 0, pcr = 1 yes tdre = 1? no continue data transmission? no tend = 1? break output? no yes yes no yes read the serial status register (ssr) and check that bit tdre is set to 1, then set bit mpbt in ssr to 0 or 1 and write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.17 example of multiprocessor data transmission flowchart 299 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1 bit tend in ssr bit is set to 1, the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.18 shows an example of the operation when transmitting using the multiprocessor format. 1 frame start bit start bit transmit data transmit data mpb mpb stop bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.18 example of operation when transmitting using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) multiprocessor receiving figure 10.19 shows an example of a flowchart for multiprocessor data reception. this procedure should be followed for multiprocessor data reception after initializing sci3. 300 start end read bits oer and fer in ssr 2 set bit mpie to 1 in scr3 1 3 4 5 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + fer = 1? no rdrf = 1? yes continue data reception? no no yes read bits oer and fer in ssr no own id? yes read bit rdrf in ssr yes oer + fer = 1? no read receive data in rdr no rdrf = 1? yes receive error processing (a) set bit mpie to 1 in scr3. read bits oer and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr and compare it with this receiver's own id. if the id is not this receiver's, set bit mpie to 1 again. when the rdr data is read, bit rdrf is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1, then read the data in rdr. if a receive error has occurred, read bits oer and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer and fer are both cleared to 0. reception cannot be resumed if either of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 3x pin. 1. 2. 3. 4. 5. figure 10.19 example of multiprocessor data reception flowchart 301 start receive error processing end of receive error processing clear bits oer and fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? no no no overrun error processing framing error processing (a) figure 10.19 example of multiprocessor data reception flowchart (cont) figure 10.20 shows an example of the operation when receiving using the multiprocessor format. 302 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 no rxi request rdr retains previous state rdr data read when data is not this receiver's id, bit mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 rxi request rdrf cleared to 0 rdr data read when data is this receiver's id, reception is continued rdr data read bit mpie set to 1 again figure 10.20 example of operation when receiving using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) 303 10.4 interrupts sci3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). these interrupts have the same vector address. the various interrupt requests are shown in table 10.13. table 10.13 sci3 interrupt requests interrupt abbreviation interrupt request vector address rxi interrupt request initiated by receive data full flag (rdrf) h'0022/h'0024 txi interrupt request initiated by transmit data empty flag (tdre) tei interrupt request initiated by transmit end flag (tend) eri interrupt request initiated by receive error flag (oer, fer, per) each interrupt request can be enabled or disabled by means of bits tie and rie in scr3. when bit tdre is set to 1 in ssr, a txi interrupt is requested. when bit tend is set to 1 in ssr, a tei interrupt is requested. these two interrupts are generated during transmission. the initial value of bit tdre in ssr is 1. therefore, if the transmit data empty interrupt request (txi) is enabled by setting bit tie to 1 in scr3 before transmit data is transferred to tdr, a txi interrupt will be requested even if the transmit data is not ready. also, the initial value of bit tend in ssr is 1. therefore, if the transmit end interrupt request (tei) is enabled by setting bit teie to 1 in scr3 before transmit data is transferred to tdr, a tei interrupt will be requested even if the transmit data has not been sent. effective use of these interrupt requests can be made by having processing that transfers transmit data to tdr carried out in the interrupt service routine. to prevent the generation of these interrupt requests (txi and tei), on the other hand, the enable bits for these interrupt requests (bits tie and teie) should be set to 1 after transmit data has been transferred to tdr. when bit rdrf is set to 1 in ssr, an rxi interrupt is requested, and if any of bits oer, per, and fer is set to 1, an eri interrupt is requested. these two interrupt requests are generated during reception. for further details, see 3.3, interrupts. 304 10.5 application notes the following points should be noted when using sci3. 1. relation between writes to tdr and bit tdre bit tdre in the serial status register (ssr) is a status flag that indicates that data for serial transmission has not been prepared in tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. when sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr irrespective of the state of bit tdre, but if new data is written to tdr while bit tdre is cleared to 0, the data previously stored in tdr will be lost of it has not yet been transferred to tsr. accordingly, to ensure that serial transmission is performed dependably, you should first check that bit tdre is set to 1, then write the transmit data to tdr once only (not two or more times). 2. operation when a number of receive errors occur simultaneously if a number of receive errors are detected simultaneously, the status flags in ssr will be set to the states shown in table 10.14. if an overrun error is detected, data transfer from rsr to rdr will not be performed, and the receive data will be lost. table 10.14 ssr status flag states and receive data transfer ssr status flags receive data transfer rdrf * oer fer per rsr rdr receive error status 1 1 0 0 x overrun error 0 0 1 0 o framing error 0 0 0 1 o parity error 1 1 1 0 x overrun error + framing error 1 1 0 1 x overrun error + parity error 0 0 1 1 o framing error + parity error 1 1 1 1 x overrun error + framing error + parity error o : receive data is transferred from rsr to rdr. x : receive data is not transferred from rsr to rdr. note: * bit rdrf retains its state prior to data reception. however, note that if rdr is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, rdrf will be cleared to 0. 305 3. break detection and processing when a framing error is detected, a break can be detected by reading the value of the rxd 3x pin directly. in a break, the input from the rxd 3x pin becomes all 0s, with the result that bit fer is set and bit per may also be set. sci3 continues the receive operation even after receiving a break. note, therefore, that even though bit fer is cleared to 0 it will be set to 1 again. 4. mark state and break detection when bit te is cleared to 0, the txd 3x pin functions as an i/o port whose input/output direction and level are determined by pdr and pcr. this fact can be used to set the txd 3x pin to the mark state, or to detect a break during transmission. to keep the communication line in the mark state (1 state) until bit te is set to 1, set pcr = 1 and pdr = 1. since bit te is cleared to 0 at this time, the txd 3x pin functions as an i/o port and 1 is output. to detect a break, clear bit te to 0 after setting pcr = 1 and pdr = 0. when bit te is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the txd 3x pin functions as an i/o port, and 0 is output from the txd 3x pin. 5. receive error flags and transmit operation (synchronous mode only) when a receive error flag (oer, per, or fer) is set to 1, transmission cannot be started even if bit tdre is cleared to 0. the receive error flags must be cleared to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if bit re is cleared to 0. 6. receive data sampling timing and receive margin in asynchronous mode in asynchronous mode, sci3 operates on a basic clock with a frequency 16 times the transfer rate. when receiving, sci3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. receive data is latched internally at the 8th rising edge of the basic clock. this is illustrated in figure 10.21. 306 0 7 15 0 7 15 0 internal basic clock receive data (rxd3x) start bit d0 16 clock pulses 8 clock pulses d1 synchronization sampling timing data sampling timing figure 10.21 receive data sampling timing in asynchronous mode consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). m ={(0.5 1 ) d 0.5 (l 0.5) f} 1/(2 307 7. relation between rdr reads and bit rdrf in a receive operation, sci3 continually checks the rdrf flag. if bit rdrf is cleared to 0 when reception of one frame ends, normal data reception is completed. if bit rdrf is set to 1, this indicates that an overrun error has occurred. when the contents of rdr are read, bit rdrf is cleared to 0 automatically. therefore, if bit rdr is read more than once, the second and subsequent read operations will be performed while bit rdrf is cleared to 0. note that, when an rdr read is performed while bit rdrf is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. this is illustrated in figure 10.22. communication line rdrf rdr frame 1 frame 2 frame 3 data 1 data 1 rdr read rdr read data 1 is read at point (a) data 2 data 3 data 2 (a) data 2 is read at point (b) (b) figure 10.22 relation between rdr read timing and data in this case, only a single rdr read operation (not two or more) should be performed after first checking that bit rdrf is set to 1. if two or more reads are performed, the data read the first time should be transferred to ram, etc., and the ram contents used. also, ensure that there is sufficient margin in an rdr read operation before reception of the next frame is completed. to be precise in terms of timing, the rdr read should be completed before bit 7 is transferred in synchronous mode, or before the stop bit is transferred in asynchronous mode. 8. transmit and receive operations when making a state transition make sure that transmit and receive operations have completely finished before carrying out state transition processing. 308 9. switching sck 3 function if pin sck 3 is used as a clock output pin by sci3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock ( ) cycle immediately after it is switched. this can be prevented by either of the following methods according to the situation. a. when an sck 3 function is switched from clock output to non clock-output when stopping data transfer, issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. in this case, bit com in smr should be left 1. the above prevents sck 3 from being used as a general input/output pin. to avoid an intermediate level of voltage from being applied to sck 3 , the line connected to sck 3 should be pulled up to the v cc level via a resistor, or supplied with output from an external device. b. when an sck 3 function is switched from clock output to general input/output when stopping data transfer, (i) issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. (ii) clear bit com in smr to 0 (iii) clear bits cke1 and cke0 in scr3 to 0 note that special care is also needed here to avoid an intermediate level of voltage from being applied to sck 3 . 10. set up at subactive or subsleep mode at subactive or subsleep mode, sci3 becomes possible use only at cpu clock is w/2. 309 section 11 14-bit pwm 11.1 overview the h8/3864 series is provided with a 14-bit pwm (pulse width modulator) on-chip, which can be used as a d/a converter by connecting a low-pass filter. 11.1.1 features features of the 14-bit pwm are as follows. ? choice of two conversion periods any of the following four conversion periods can be chosen: 131,072/? with a minimum modulation width of 8/?(pwcr1 = 1, pwcr0 = 1) 65,536/? with a minimum modulation width of 4/?(pwcr1 = 1, pwcr0 = 0) 32,768/? with a minimum modulation width of 2/?(pwcr1 = 0, pwcr0 = 1) 16,384/? with a minimum modulation width of 1/?(pwcr1 = 0, pwcr0 = 0) ? pulse division method for less ripple ? use of module standby mode enables this module to be placed in standby mode independently when not used. 11.1.2 block diagram figure 11.1 shows a block diagram of the 14-bit pwm. 310 internal data bus pwdrl pwdru pwcr pwm waveform generator ?2 ?4 ?8 ?16 notation: pwdrl: pwdru: pwcr: pwm data register l pwm data register u pwm control register pwm figure 11.1 block diagram of the 14 bit pwm 11.1.3 pin configuration table 11.1 shows the output pin assigned to the 14-bit pwm. table 11.1 pin configuration name abbrev. i/o function pwm output pin pwm output pulse-division pwm waveform output 11.1.4 register configuration table 11.2 shows the register configuration of the 14-bit pwm. table 11.2 register configuration name abbrev. r/w initial value address pwm control register pwcr w h'fc h'ffd0 pwm data register u pwdru w h'c0 h'ffd1 pwm data register l pwdrl w h'00 h'ffd2 clock stop register 2 ckstpr2 r/w h'ff h'fffb 311 11.2 register descriptions 11.2.1 pwm control register (pwcr) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr0 0 w 2 1 1 pwcr1 0 w pwcr is an 8-bit write-only register for input clock selection. upon reset, pwcr is initialized to h'fc. bits 7 to 2: reserved bits bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. bits 1 and 0: clock select 1 and 0 (pwcr1, pwcr0) bits 1 and 0 select the clock supplied to the 14-bit pwm. these bits are write-only bits; they are always read as 1. bit 1 pwcr1 bit 0 pwcr0 description 0 0 the input clock is /2 (t * = 2/ ) (initial value) the conversion period is 16,384/ , with a minimum modulation width of 1/ 0 1 the input clock is /4 (t * = 4/ ) the conversion period is 32,768/ , with a minimum modulation width of 2/ 1 0 the input clock is /8 (t * = 8/ ) the conversion period is 65,536/ , with a minimum modulation width of 4/ 1 1 the input clock is /16 (t * = 16/ ) the conversion period is 131,072/ , with a minimum modulation width of 8/ note: * period of pwm input clock. 312 11.2.2 pwm data registers u and l (pwdru, pwdrl) bit initial value read/write 7 1 6 1 5 pwdru5 0 w 4 pwdru4 0 w 3 pwdru3 0 w 0 pwdru0 0 w 2 pwdru2 0 w 1 pwdru1 0 w pwdru bit initial value read/write 7 pwdrl7 0 w 6 pwdrl6 0 w 5 pwdrl5 0 w 4 pwdrl4 0 w 3 pwdrl3 0 w 0 pwdrl0 0 w 2 pwdrl2 0 w 1 pwdrl1 0 w pwdrl pwdru and pwdrl form a 14-bit write-only register, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. the value written to pwdru and pwdrl gives the total high- level width of one pwm waveform cycle. when 14-bit data is written to pwdru and pwdrl, the register contents are latched in the pwm waveform generator, updating the pwm waveform generation data. the 14-bit data should always be written in the following sequence: 1. write the lower 8 bits to pwdrl. 2. write the upper 6 bits to pwdru. pwdru and pwdrl are write-only registers. if they are read, all bits are read as 1. upon reset, pwdru and pwdrl are initialized to h'c000. 11.2.3 clock stop register 2 (ckstpr2) wdckstp pwckstp ldckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the pwm is described here. for details of the other bits, see the sections on the relevant modules. 313 bit 1: pwm module standby mode control (pwckstp) bit 1 controls setting and clearing of module standby mode for the pwm. pwckstp description 0 pwm is set to module standby mode 1 pwm module standby mode is cleared (initial value) 314 11.3 operation 11.3.1 operation when using the 14-bit pwm, set the registers in the following sequence. 1. set bit pwm in port mode register 3 (pmr3) to 1 so that pin p3 0 /pwm is designated for pwm output. 2. set bits pwcr1 and pwcr0 in the pwm control register (pwcr) to select a conversion period of 131,072/?(pwcr1 = 1, pwcr0 = 1), 65,536/?(pwcr1 = 1, pwcr0 = 0), 32,768/?(pwcr1 = 0, pwcr0 = 1), or 16,384/?(pwcr1 = 0, pwcr0 = 0). 3. set the output waveform data in pwm data registers u and l (pwdru/l). be sure to write in the correct sequence, first pwdrl then pwdru. when data is written to pwdru, the data in these registers will be latched in the pwm waveform generator, updating the pwm waveform generation in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 11.2. the total of the high- level pulse widths during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be represented as follows. t h = (data value in pwdru and pwdrl + 64) t /2 where t?is the pwm input clock period: 2/?(pwcr = h'0), 4/?(pwcr = h'1), 8/?(pwcr = h'2), or 16/?(pwcr = h'3). example: settings in order to obtain a conversion period of 32,768 ?: when pwcr1 = 0 and pwcr0 = 0, the conversion period is 16,384/? so ?must be 0.5 mhz. in this case, tfn = 512 ?, with 1/?(resolution) = 2.0 ?. when pwcr1 = 0 and pwcr0 = 1, the conversion period is 32,768/? so ?must be 1 mhz. in this case, tfn = 512 ?, with 2/?(resolution) = 2.0 ?. when pwcr1 = 1 and pwcr0 = 0, the conversion period is 65,536/?, so ?must be 2 mhz. in this case, tfn = 512 ?, with 4/?(resolution) = 2.0 ?. accordingly, for a conversion period of 32,768 ?, the system clock frequency (? must be 0.5 mhz, 1 mhz, or 2 mhz. 315 1 conversion period t f1 t f2 t f63 t f64 t h1 t h2 t h3 t h63 t h64 t = t + t + t + t = t = t h h1 h2 h3 h64 ..... t f1 f2 f3 ..... = t f84 figure 11.2 pwm output waveform 11.3.2 pwm operation modes pwm operation modes are shown in table 11.3. table 11.3 pwm operation modes operation mode reset active sleep watch subactive subsleep standby module standby pwcr reset functions functions held held held held held pwdru reset functions functions held held held held held pwdrl reset functions functions held held held held held 316 317 section 12 a/d converter 12.1 overview the h8/3864 series includes on-chip a resistance-ladder-based successive-approximation analog- to-digital converter, and can convert up to 8 channels of analog input. 12.1.1 features the a/d converter has the following features. ? 10-bit resolution ? eight input channels ? conversion time: approx. 15.5 ? per channel (at 2 mhz operation) ? built-in sample-and-hold function ? interrupt requested on completion of a/d conversion ? a/d conversion can be started by external trigger input ? use of module standby mode enables this module to be placed in standby mode independently when not used. 318 12.1.2 block diagram figure 12.1 shows a block diagram of the a/d converter. internal data bus amr adsr adrrh adrrl control logic + com- parator an an an an an an an an adtrg av av cc ss multiplexer reference voltage irrad av cc av ss 0 1 2 3 4 5 6 7 notation: amr: adsr: adrr: irrad: a/d mode register a/d start register a/d result register a/d conversion end interrupt request flag figure 12.1 block diagram of the a/d converter 319 12.1.3 pin configuration table 12.1 shows the a/d converter pin configuration. table 12.1 pin configuration name abbrev. i/o function analog power supply avcc input power supply and reference voltage of analog part analog ground avss input ground and reference voltage of analog part analog input 0 an0 input analog input channel 0 analog input 1 an1 input analog input channel 1 analog input 2 an2 input analog input channel 2 analog input 3 an3 input analog input channel 3 analog input 4 an4 input analog input channel 4 analog input 5 an5 input analog input channel 5 analog input 6 an6 input analog input channel 6 analog input 7 an7 input analog input channel 7 external trigger input adtrg input external trigger input for starting a/d conversion 12.1.4 register configuration table 12.2 shows the a/d converter register configuration. table 12.2 register configuration name abbrev. r/w initial value address a/d mode register amr r/w h'30 h'ffc6 a/d start register adsr r/w h'7f h'ffc7 a/d result register h adrrh r not fixed h'ffc4 a/d result register l adrrl r not fixed h'ffc5 clock stop register 1 ckstprt1 r/w h'ff h'fffa 320 12.2 register descriptions 12.2.1 a/d result registers (adrrh, adrrl) bit 7 6 5 4 3 adrrh adrrl 0 21 76543 0 21 initial value read/write not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r adr9 adr8 adr7 adr6 adr5 adr2 adr4 adr3 adr1 adr0 adrrh and adrrl together comprise a 16-bit read-only register for holding the results of analog-to-digital conversion. the upper 8 bits of the data are held in adrrh, and the lower 2 bits in adrrl. adrrh and adrrl can be read by the cpu at any time, but the adrrh and adrrl values during a/d conversion are not fixed. after a/d conversion is complete, the conversion result is stored as 10-bit data, and this data is held until the next conversion operation starts. adrrh and adrrl are not cleared on reset. 12.2.2 a/d mode register (amr) bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 5 1 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w amr is an 8-bit read/write register for specifying the a/d conversion speed, external trigger option, and the analog input pins. upon reset, amr is initialized to h'30. 321 bit 7: clock select (cks) bit 7 sets the a/d conversion speed. bit 7 conversion time cks conversion period ?= 1 mhz ?= 5 mhz 0 62/ (initial value) 62 s 31 s 1 31/ 31 s 15.5 s * note: * operation is not guaranteed if the conversion time is less than 15.5 s. set bit 7 for a value of at least 15.5 s. bit 6: external trigger select (trge) bit 6 enables or disables the start of a/d conversion by external trigger input. bit 6 trge description 0 disables start of a/d conversion by external trigger (initial value) 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg * note: * the external trigger ( adtrg ) edge is selected by bit integ4 of iegr. see 1. interrupt edge select register (iegr) in 3.3.2 for details. bits 5 and 4: reserved bits bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. 322 bits 3 to 0: channel select (ch3 to ch0) bits 3 to 0 select the analog input channel. the channel selection should be made while bit adsf is cleared to 0. bit 3 ch3 bit 2 ch2 bit 1 ch1 bit 0 ch0 analog input channel 00 ** no channel selected (initial value) 0100an0 0101an1 0110an2 0111an3 1000an4 1001an5 1010an6 1011an7 note: * don t care 12.2.3 a/d start register (adsr) bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf) or by input of the designated edge of the external trigger signal, which also sets adsf to 1. when conversion is complete, the converted data is set in adrrh and adrrl, and at the same time adsf is cleared to 0. 323 bit 7: a/d start flag (adsf) bit 7 controls and indicates the start and end of a/d conversion. bit 7 adsf description 0 read: indicates the completion of a/d conversion (initial value) write: stops a/d conversion 1 read: indicates a/d conversion in progress write: starts a/d conversion bits 6 to 0: reserved bits bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 12.2.4 clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the a/d converter is described here. for details of the other bits, see the sections on the relevant modules. bit 4: a/d converter module standby mode control (adckstp) bit 4 controls setting and clearing of module standby mode for the a/d converter. adckstp description 0 a/d converter is set to module standby mode 1 a/d converter module standby mode is cleared (initial value) 324 12.3 operation 12.3.1 a/d conversion operation the a/d converter operates by successive approximations, and yields its conversion result as 10- bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 2 (irr2) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 2 (ienr2) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 start of a/d conversion by external trigger input the a/d converter can be made to start a/d conversion by input of an external trigger signal. external trigger input is enabled at pin adtrg when bit irq4 in pmr1 is set to 1 and bit trge in amr is set to 1. then when the input signal edge designated in bit ieg4 of interrupt edge select register (iegr) is detected at pin adtrg , bit adsf in adsr will be set to 1, starting a/d conversion. figure 12.2 shows the timing. pin adtrg (when bit ieg4 = 0) adsf a/d conversion figure 12.2 external trigger input timing 325 12.3.3 a/d converter operation modes a/d converter operation modes are shown in table 12.3. table 12.3 a/d converter operation modes operation mode reset active sleep watch subactive subsleep standby module standby amr reset functions functions held held held held held adsr reset functions functions held held held held held adrrh held * functions functions held held held held held adrrl held * functions functions held held held held held note: * undefined in a power-on reset. 12.4 interrupts when a/d conversion ends (adsf changes from 1 to 0), bit irrad in interrupt request register 2 (irr2) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 2 (ienr2). for further details see 3.3, interrupts. 12.5 typical use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 12.3 shows the operation timing. 1. bits ch3 to ch0 of the a/d mode register (amr) are set to 0101, making pin an 1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is complete, bit irrad is set to 1, and the a/d conversion result is stored is stored in adrrh and adrrl. at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place. 326 figures 12.4 and 12.5 show flow charts of procedures for using the a/d converter. idle a/d conversion (1) idle a/d conversion (2) idle interrupt (irrad) ienad adsf channel 1 (an 1 ) operation state adrrh adrrl set * set * set * read conversion result read conversion result a/d conversion result (1) a/d conversion result (2) a/d conversion starts note: ( ) indicates instruction execution by software. * figure 12.3 typical a/d converter operation timing 327 start set a/d conversion speed and input channel perform a/d conversion? end yes no disable a/d conversion end interrupt start a/d conversion adsf = 0? no yes read adsr read adrrh/adrrl data figure 12.4 flow chart of procedure for using a/d converter (polling by software) 328 start set a/d conversion speed and input channels enable a/d conversion end interrupt start a/d conversion a/d conversion end interrupt? yes no end yes no clear bit irrad to 0 in irr2 read adrrh/adrrl data perform a/d conversion? figure 12.5 flow chart of procedure for using a/d converter (interrupts used) 12.6 application notes ? data in adrrh and adrrl should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. ? changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. ? when a/d conversion is started after clearing module standby mode, wait for 10 ?clock cycles before starting. 329 section 13 lcd controller/driver 13.1 overview the h8/3867 series and h8/3827 series has an on-chip segment type lcd control circuit, lcd driver, and power supply circuit, enabling it to directly drive an lcd panel. 13.1.1 features 1. features features of the lcd controller/driver are given below. ? display capacity duty cycle internal driver segment external expansion driver static 32 seg 256 seg 1/2 32 seg 128 seg 1/3 32 seg 64 seg 1/4 32 seg 64 seg ? lcd ram capacity 8 bits 32 bytes (256 bits) ? word access to lcd ram ? all eight segment output pins can be used individually as port pins. ? common output pins not used because of the duty cycle can be used for common double- buffering (parallel connection). ? display possible in operating modes other than standby mode ? choice of 11 frame frequencies ? built-in power supply split-resistance, supplying lcd drive power ? use of module standby mode enables this module to be placed in standby mode independently when not used. ? built-in step-up constant-voltage (5 v) power supply allows lcd display even at low voltages. (h8/3867 series) ? a or b waveform selectable by software 330 13.1.2 block diagram figure 13.1 shows a block diagram of the lcd controller/driver. ?2 to ?256 w cl 2 cl 1 seg n, do lpcr lcr lcr2 display timing generator lcd ram (32 bytes) internal data bus 32-bit shift register lcd drive power supply (built-in step-up constant- voltage circuit) segment driver common data latch common driver m v 1 v 2 v 3 v ss com 1 com 4 seg 32 /cl 1 seg 31 /cl 2 seg 30 /do seg 29 /m seg 28 seg 1 notation: lpcr: lcd port control register lcr: lcd control register lcr2: lcd control register 2 v 0 figure 13.1 block diagram of lcd controller/driver 331 13.1.3 pin configuration table 13.1 shows the lcd controller/driver pin configuration. table 13.1 pin configuration name abbrev. i/o function segment output pins seg 32 to seg 1 output lcd segment drive pins all pins are multiplexed as port pins (setting programmable) common output pins com 4 to com 1 output lcd common drive pins pins can be used in parallel with static or 1/2 duty segment external expansion signal pins cl 1 output display data latch clock, multiplexed as seg 32 cl 2 output display data shift clock, multiplexed as seg 31 m output lcd alternation signal, multiplexed as seg 29 do output serial display data, multiplexed as seg 30 lcd power supply pins v 0 , v 1 , v 2 , v 3 used when a bypass capacitor is connected externally, and when an external power supply circuit is used 13.1.4 register configuration table 13.2 shows the register configuration of the lcd controller/driver. table 13.2 lcd controller/driver registers name abbrev. r/w initial value address lcd port control register lpcr r/w h'00 h'ffc0 lcd control register lcr r/w h'80 h'ffc1 lcd control register 2 lcr2 r/w h'60 h'ffc2 lcd ram r/w undefined h'f740, h'f75f clock stop register 2 ckstpr2 r/w h'ff h'fffb 332 13.2 register descriptions 13.2.1 lcd port control register (lpcr) b it i nitial value r ead/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 4 sgx 0 r/w 3 sgs3 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w lpcr is an 8-bit read/write register which selects the duty cycle and lcd driver pin functions. lpcr is initialized to h'00 upon reset. bits 7 to 5: duty cycle select 1 and 0 (dts1, dts0), common function select (cmx) the combination of dts1 and dts0 selects static, 1/2, 1/3, or 1/4 duty. cmx specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. bit 7 dts1 bit 6 dts0 bit 5 cmx duty cycle common drivers notes 0 0 0 static com 1 (initial value) do not use com 4 , com 3 , and com 2 . 1 com 4 to com 1 com 4 , com 3 , and com 2 output the same waveform as com 1 . 0 1 0 1/2 duty com 2 to com 1 do not use com 4 and com 3 . 1 com 4 to com 1 com 4 outputs the same waveform as com 3 , and com 2 outputs the same waveform as com 1 . 1 0 0 1/3 duty com 3 to com 1 do not use com 4 . 1 com 4 to com 1 do not use com 4 . 1 1 0 1/4 duty com 4 to com 1 1 333 bit 4: expansion signal select (sgx) bit 4 selects whether the seg 32 /cl 1 , seg 31 /cl 2 , seg 30 /do, and seg 29 /m pins are used as segment pins (seg 32 to seg 29 ) or as segment external expansion pins (cl 1 , cl 2 , do, m). bit 4 sgx description 0 pins seg 32 to seg 29 * (initial value) 1 pins cl 1 , cl 2 , do, m note: * these pins function as ports when the setting of sgs3 to sgs0 is 0000 or 0001. bit 3: segment driver select 3 to 0 (sgs3 to sgs0) bits 3 to 0 select the segment drivers to be used. function of pins seg 32 to seg 1 bit 4 sgx bit 3 sgs3 bit 2 sgs2 bit 1 sgs1 bit 0 sgs0 seg 32 to seg 25 seg 24 to seg 17 seg 16 to seg 9 seg 8 to seg 1 notes 0 0 0 0 0 port port port port (initial value) 0 0 0 1 port port port port 001 * seg port port port 010 * seg seg port port 011 * seg seg seg port 1 ** * seg seg seg seg 1 0 0 0 0 port * port port port **** setting prohibited * : don t care note: * seg 32 to seg 29 are external expansion pins. 334 13.2.2 lcd control register (lcr) b it i nitial value r ead/write 7 1 6 psw 0 r/w 5 act 0 r/w 4 disp 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w lcr is an 8-bit read/write register which performs lcd drive power supply on/off control and display data control, and selects the frame frequency. lcr is initialized to h'80 upon reset. bit 7: reserved bit bit 7 is reserved; it is always read as 1 and cannot be modified. bit 6: lcd drive power supply on/off control (psw) bit 6 can be used to turn the lcd drive power supply off when lcd display is not required in a power-down mode, or when an external power supply is used. when the act bit is cleared to 0, or in standby mode, the lcd drive power supply is turned off regardless of the setting of this bit. bit 6 psw description 0 lcd drive power supply off (initial value) 1 lcd drive power supply on bit 5: display function activate (act) bit 5 specifies whether or not the lcd controller/driver is used. clearing this bit to 0 halts operation of the lcd controller/driver. the lcd drive power supply is also turned off, regardless of the setting of the psw bit. however, register contents are retained. bit 5 act description 0 lcd controller/driver operation halted (initial value) 1 lcd controller/driver operates 335 bit 4: display data control (disp) bit 4 specifies whether the lcd ram contents are displayed or blank data is displayed regardless of the lcd ram contents. bit 4 disp description 0 blank data is displayed (initial value) 1 lcd ram data is display bits 3 to 0: frame frequency select 3 to 0 (cks3 to cks0) bits 3 to 0 select the operating clock and the frame frequency. in subactive mode, watch mode, and subsleep mode, the system clock (? is halted, and therefore display operations are not performed if one of the clocks from ?2 to ?256 is selected. if lcd display is required in these modes, ?, ?/2, or ?/4 must be selected as the operating clock. bit 3 bit 2 bit 1 bit 0 frame frequency * 2 cks3 cks2 cks1 cks0 operating clock ?= 2 mhz ?= 250 khz * 1 0 * 00 w 128 hz * 3 (initial value) 0 * 01 w/2 64 hz * 3 0 * 1 * w/4 32 hz * 3 1000 /2 244 hz 1001 /4 977 hz 122 hz 1010 /8 488 hz 61 hz 1011 /16 244 hz 30.5 hz 1100 /32 122 hz 1101 /64 61 hz 1110 /128 30.5 hz 1111 /256 * : don t care notes: 1. this is the frame frequency in active (medium-speed, osc/16) mode when = 2 mhz. 2. when 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 3. this is the frame frequency when w = 32.768 khz. 336 13.2.3 lcd control register 2 (lcr2) b it i nitial value r ead/write 7 lcdab 0 r/w 6 1 5 1 4 sups 0 r/w 3 cds3 0 r/w 0 cds0 0 r/w 2 cds2 0 r/w 1 cds1 0 r/w lcr2 is an 8-bit read/write register which controls switching between the a waveform and b waveform, selects the drive power supply, controls the step-up constant-voltage (5 v) power supply, and selects the duty cycle of the charge/discharge pulses which control disconnection of the power supply split-resistance from the power supply circuit. lcr2 is initialized to h'60 upon reset. bit 7: a waveform/b waveform switching control (lcdab) bit 7 specifies whether the a waveform or b waveform is used as the lcd drive waveform. bit 7 lcdab description 0 drive using a waveform (initial value) 1 drive using b waveform bits 6 and 5: reserved bits bits 6 and 5 are reserved; they are always read as 1 and cannot be modified. bit 4: drive power supply select, step-up constant-voltage (5 v) power supply control (sups) (applies to the h8/3867 series only) when v cc is selected as the drive power supply, the step-up constant-voltage (5 v) power supply simultaneously stops operating; when 5 v is selected as the drive power supply, the step-up constant-voltage (5 v) power supply simultaneously operates. bit 4 sups description 0 drive power supply is v cc , step-up constant-voltage (5 v) power supply halts (initial value) 1 drive power supply is 5 v, step-up constant-voltage (5 v) power supply operates 337 bits 3 to 0: charge/discharge pulse duty cycle select (cds3 to cds0) bit 3 cds3 bit 2 cds2 bit 1 cds1 bit 0 cds0 duty cycle notes 0 0 0 0 1 fixed high (initial value) 00011/8 00102/8 00113/8 01004/8 01015/8 01106/8 0 1 1 1 0 fixed low 10 ** 1/16 11 ** 1/32 * : don t care bits 3 to 0 select the duty cycle while the power supply split-resistance is connected to the power supply circuit. when a 0 duty cycle is selected, the power supply split-resistance is permanently disconnected from the power supply circuit, so power should be supplied to pins v1, v2, and v3 by an external circuit. figure 13.2 shows the waveform of the charge/discharge pulses. the duty cycle is tc/tw. com1 charge/discharge pulses tc tdc t w 1 frame tc tdc : power supply split-resistance connected : power supply split-resistance disconnected figure 13.2 example of a waveform with 1/2 duty and 1/2 bias 338 13.2.4 clock stop register 2 (ckstpr2) b it i nitial value r ead/write 7 1 6 1 5 1 4 1 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 wdckstp 1 r/w 1 pwckstp 1 r/w ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the lcd controller/driver is described here. for details of the other bits, see the sections on the relevant modules. bit 0: lcd controller/driver module standby mode control (ldckstp) bit 0 controls setting and clearing of module standby mode for the lcd controller/driver. bit 0 ldckstp description 0 lcd controller/driver is set to module standby mode 1 lcd controller/driver module standby mode is cleared (initial value) 339 13.3 operation 13.3.1 settings up to lcd display to perform lcd display, the hardware and software related items described below must first be determined. 1. hardware settings a. using 1/2 duty when 1/2 duty is used, interconnect pins v 2 and v 3 as shown in figure 13.3. v cc v 1 v 2 v 3 v ss v 0 figure 13.3 handling of lcd drive power supply when using 1/2 duty b. large-panel display as the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a large panel. if the display lacks sharpness when using a large panel, refer to section 13.3.7, boosting the lcd drive power supply. when static or 1/2 duty is selected, the common output drive capability can be increased. set cmx to 1 when selecting the duty cycle. in this mode, with a static duty cycle pins com 4 to com 1 output the same waveform, and with 1/2 duty the com 1 waveform is output from pins com 2 and com 1 , and the com 2 waveform is output from pins com 4 and com 3 . c. luminance adjustment function (v 0 pin) connecting a resistance between the v 0 and v 1 pins enables the luminance to be adjusted. for details, see 13.3.3, luminance adjustment function (v 0 pin). d. lcd drive power supply setting with the h8/3867 series, there are two ways of providing lcd power: by using the on- chip power supply circuit, or by using an external circuit. with the h8/3867 series, the on- chip power supply circuit allows the selection of either the power supply voltage (v cc ) or a step-up constant voltage (5 v). for details of the step-up constant-voltage power supply, see 13.3.4, step-up constant-voltage (5 v) power supply. 340 when the on-chip power supply circuit is used for the lcd drive power supply, the v 0 and v 1 pins should be interconnected externally, as shown in figure 13.4 (a). when an external power supply circuit is used for the lcd drive power supply, connect the external power supply to the v 1 pin, and short the v 0 pin to v cc externally, as shown in figure 13.4 (b). v cc v 1 v 2 v 3 v ss v 0 (a) using on-chip power supply circuit v cc v 1 v 2 v 3 v ss v 0 (b) using external power supply circuit external power supply figure 13.4 examples of lcd power supply pin connections e. low-power-consumption lcd drive system use of a low-power-consumption lcd drive system enables the power consumption required for lcd drive to be optimized. for details, see 13.3.5, low-power-consumption lcd drive system. f. segment external expansion the number of segments can be increased by connecting an hd66100 externally. for details, see section 13.3.8, connection to hd66100. 341 2. software settings a. duty selection any of four duty cycles?tatic, 1/2 duty, 1/3 duty, or 1/4 duty?an be selected with bits dts1 and dts0. b. segment selection the segment drivers to be used can be selected with bits sgs 3 to sgs 0 . c. frame frequency selection the frame frequency can be selected by setting bits cks 3 to cks 0 . the frame frequency should be selected in accordance with the lcd panel specification. for the clock selection method in watch mode, subactive mode, and subsleep mode, see 13.3.6, operation in power-down modes. d. a or b waveform selection either the a or b waveform can be selected as the lcd waveform to be used by means of lcdab. e. lcd drive power supply selection when the on-chip power supply circuit is used, the power supply to be used can be selected with the sups bit. when an external power supply circuit is used, select v cc with the sups bit and turn the lcd drive power supply off with the psw bit. 342 13.3.2 relationship between lcd ram and display the relationship between the lcd ram and the display segments differs according to the duty cycle. lcd ram maps for the different duty cycles when segment external expansion is not used are shown in figures 13.5 to 13.8, and lcd ram maps when segment external expansion is used in figures 13.9 to 13.12. after setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary ram, and display is started automatically when turned on. word- or byte-access instructions can be used for ram setting. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 2 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 seg 1 seg 32 h 'f740 h 'f74f seg 32 seg 32 seg 32 seg 31 seg 31 seg 31 seg 31 com 4 com 3 com 2 com 1 com 4 com 3 com 2 com 1 figure 13.5 lcd ram map when not using segment external expansion (1/4 duty) 343 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 h'f740 h'f74f seg 32 seg 32 seg 32 seg 31 seg 31 seg 31 com 3 com 2 com 1 com 3 com 2 com 1 space not used for display figure 13.6 lcd ram map when not using segment external expansion (1/3 duty) 344 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 4 seg 4 seg 3 seg 3 seg 2 seg 2 seg 1 seg 1 seg 32 h'f740 h'f747 h'f74f seg 32 seg 31 seg 31 seg 30 seg 30 seg 29 seg 29 com 2 com 1 com 2 com 1 com 2 com 1 com 2 com 1 display space space not used for display figure 13.7 lcd ram map when not using segment external expansion (1/2 duty) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 32 h'f740 h'f743 h'f74f seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 com 1 com 1 com 1 com 1 com 1 com 1 com 1 com 1 space not used for display display space figure 13.8 lcd ram map when not using segment external expansion (static mode) 345 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 2 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 seg 1 seg 64 h'f740 h'f75f seg 64 seg 64 seg 64 seg 63 seg 63 seg 63 seg 63 com 4 com 3 com 2 com 1 com 4 com 3 com 1 com 1 expansion driver display space figure 13.9 lcd ram map when using segment external expansion (sgx = ?? sgs3 to sgs0 = ?000?1/4 duty) 346 space not used for display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 h'f740 h'f75f seg 64 seg 64 seg 64 seg 63 seg 63 seg 63 com 3 com 2 com 1 com 3 com 1 com 1 expansion driver display space figure 13.10 lcd ram map when using segment external expansion (sgx = ?? sgs3 to sgs0 = ?000?1/3 duty) 347 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 4 seg 4 seg 3 seg 3 seg 2 seg 2 seg 1 seg 1 seg 128 h'f740 h'f75f seg 128 seg 127 seg 127 seg 126 seg 126 seg 125 seg 125 com 2 com 1 com 2 com 1 com 2 com 1 com 2 com 1 expansion driver display space figure 13.11 lcd ram map when using segment external expansion (sgx = ?? sgs3 to sgs0 = ?000?1/2 duty) 348 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 256 h'f740 h'f75f seg 255 seg 254 seg 253 seg 252 seg 251 seg 250 seg 249 com 1 com 1 com 1 com 1 com 1 com 1 com 1 com 1 expansion driver display space figure 13.12 lcd ram map when using segment external expansion (sgx = ?? sgs3 to sgs0 = ?000?static) 349 13.3.3 luminance adjustment function (v0 pin) figure 13.13 shows a detailed block diagram of the lcd drive power supply unit. the voltage output to the v 0 pin is either v cc or the 5 v output from the step-up conversion power supply circuit. when either of these voltages is used directly as the lcd drive power supply, the v 0 and v 1 pins should be shorted. also, connecting a variable resistance, r, between the v 0 and v 1 pins makes it possible to adjust the voltage applied to the v 1 pin, and so to provide luminance adjustment for the lcd panel. power supply selector * step-up constant- voltage power supply * applies to the h8/3867 series v cc v ss 5v v 0 v 1 v 2 v 3 r figure 13.13 lcd drive power supply unit 350 13.3.4 step-up constant-voltage (5 v) power supply the h8/3867 series has an on-chip step-up constant-voltage (5 v) power supply which enables a 5 v constant voltage to be obtained independently of v cc . this feature is not provided in the h8/3827 series. when the sups bit is set to 1 in lcd control register 2 (lcr2), the step-up constant-voltage (5 v) power supply operates, and a 5 v constant voltage is output from the v 0 pin. either short the v 0 and v 1 pins or connect a resistance to divide the voltage. note: the step-up constant-voltage (5 v) power supply must not be used for any purpose other than the h8/3864 series lcd drive power supply. when a large panel is driven, the power supply capacity may be insufficient. in this case, either use v cc as the power supply or use an external power supply circuit. 13.3.5 low-power-consumption lcd drive system the use of the built-in split-resistance is normally the easiest method for implementing the lcd power supply circuit, but since the built-in resistance is fixed, a certain direct current flows constantly from the built-in resistance s v cc to v ss . as this current does not depend on the current dissipation of the lcd panel, if an lcd panel with a small current dissipation is used, a wasteful amount of power will be consumed. the h8/3864 series is equipped with a function to minimize this waste of power. use of this function makes it possible to achieve the optimum power supply circuit for the lcd panel s current dissipation. 1. principles a. capacitors are connected as external circuits to lcd power supply pins v1, v2, and v3, as shown in figure 13.14. b. the capacitors connected to v1, v2, and v3 are repeatedly charged and discharged in the cycle shown in figure 13.14, maintaining the potentials. c. at this time, the charged potential is a potential corresponding to the v1, v2, and v3 pins, respectively. (for example, with 1/3 bias drive, the charge for v2 is 2/3 that of v1, and that for v3 is 1/3 that of v1.) d. power is supplied to the lcd panel by means of the charges accumulated in these capacitors. e. the capacitances and charging/discharging periods of these capacitors are therefore determined by the current dissipation of the lcd panel. f. the charging and discharging periods can be selected by software. 351 2. example of operation (with 1/3 bias drive) a. during charging period tc in the figure, the potential is divided among pins v1, v2, and v3 by the built-in split-resistance (the potential of v2 being 2/3 that of v1, and that of v3 being 1/3 that of v1), as shown in figure 13.14, and external capacitors c1, c2, and c3 are charged. the lcd panel is continues to be driven during this time. b. in the following discharging period, tdc, charging is halted and the charge accumulated in each capacitor is discharged, driving the lcd panel. c. at this time, a slight voltage drop occurs due to the discharging; optimum values must be selected for the charging period and the capacitor capacitances to ensure that this does not affect the driving of the lcd panel. d. in this way, the capacitors connected to v1, v2, and v3 are repeatedly charged and discharged in the cycle shown in figure 13.14, maintaining the potentials and continuously driving the lcd panel. e. as can be seen from the above description, the capacitances and charging/discharging periods of the capacitors are determined by the current dissipation of the lcd panel used. the charging/discharging periods can be selected with bits cds3 to cds0. f. the actual capacitor capacitances and charging/discharging periods must be determined experimentally in accordance with the current dissipation requirements of the lcd panel. an optimum current value can be selected, in contrast to the case in which a direct current flows constantly in the built-in split-resistance. v0 v1 v2 v3 c3 c2 c1 v1 potential v2 potential v3 potential charging period tc discharging period tdc vd1 vd2 vd3 voltage drop associated with discharging due to lcd panel driving v1 2/3 v1 1/3 power supply voltage fluctuation in 1/3 bias system figure 13.14 example of low-power-consumption lcd drive operation 352 1 frame m data com 1 com 2 com 3 com 4 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty 1 frame m data com 1 com 2 com 3 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame m data com 1 com 2 seg n v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss 1 frame m data com 1 seg n v 1 v ss v 1 v ss (b) waveform with 1/3 duty (c) waveform with 1/2 duty (d) waveform with static output figure 13.15 output waveforms for each duty cycle (a waveform) 353 m data com 1 com 2 seg n v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss m data com 1 seg n v 1 v ss v 1 v ss (c) waveform with 1/2 duty (d) waveform with static output 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame (b) waveform with 1/3 duty m data com 3 seg n com 1 v 1 v 2 v 3 v ss com 2 v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty m data com 1 com 2 com 3 com 4 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame v 1 v 2, v 3 v ss figure 13.16 output waveforms for each duty cycle (b waveform) 354 table 13.3 output levels data 0 0 1 1 m0101 static common output v 1 v ss v 1 v ss segment output v 1 v ss v ss v 1 1/2 duty common output v 2 , v 3 v 2 , v 3 v 1 v ss segment output v 1 v ss v ss v 1 1/3 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 1/4 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 13.3.6 operation in power-down modes in the h8/3867 series, the lcd controller/driver can be operated even in the power-down modes. the operating state of the lcd controller/driver in the power-down modes is summarized in table 13.4. in subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless w, w/2, or w/4 has been selected by bits cks3 to cks0, the clock will not be supplied and display will halt. since there is a possibility that a direct current will be applied to the lcd panel in this case, it is essential to ensure that w, w/2, or w/4 is selected. in active (medium-speed) mode, the system clock is switched, and therefore cks3 to cks0 must be modified to ensure that the frame frequency does not change. table 13.4 power-down modes and display operation mode reset active sleep watch sub- active sub- sleep standby module standby clock runs runs runs stops stops stops stops stops * 4 w runs runs runs runs runs runs stops * 1 stops * 4 display act = 0 stops stops stops stops stops stops stops * 2 stops operation act = 1 stops functions functions functions * 3 functions * 3 functions * 3 stops * 2 stops notes: 1. the subclock oscillator does not stop, but clock supply is halted. 2. the lcd drive power supply is turned off regardless of the setting of the psw bit. 3. display operation is performed only if w, w/2, or w/4 is selected as the operating clock. 4. the clock supplied to the lcd stops. 355 13.3.7 boosting the lcd drive power supply when a large panel is driven, the on-chip power supply capacity may be insufficient. if the power supply capacity is insufficient when using the step-up constant power supply (5 v), either use v cc as the power supply or use an external power supply circuit. if the power supply capacity is insufficient when v cc is used as the power supply, the power supply impedance must be reduced. this can be done by connecting bypass capacitors of around 0.1 to 0.3 ? to pins v 1 to v 3 , as shown in figure 13.17, or by adding a split-resistance externally. h8/3864 series v cc v ss v 1 v 2 v 3 r r r r = several k ? to several m ? c= 0.1 to 0.3 f v 0 figure 13.17 connection of external split-resistance 356 13.3.8 connection to hd66100 if the segments are to be expanded externally, an hd66100 should be connected. connecting one hd66100 provides 80-segment expansion. when carrying out external expansion, select the external expansion signal function of pins seg 32 to seg 29 with the sgx bit in lpcr, and set bits sgs3 to sgs0 to 0000 or 0001. data is output externally from seg 1 of the lcd ram. seg 28 to seg 1 function as ports. figure 13.18 shows examples of connection to an hd66100. the output level is determined by a combination of the data and the m pin output, but these combinations differ from those in the hd66100. table 13.3 shows the output levels of the lcd drive power supply, and figures 13.15 and 13.16 show the common and segment waveforms for each duty cycle. when act is cleared to 0, operation stops with cl 2 = 0, cl 1 = 0, m = 0, and do at the data value (1 or 0) being output at that instant. in standby mode, the expansion pins go to the high- impedance (floating) state. when external expansion is implemented, the load in the lcd panel increases and the on-chip power supply may not provide sufficient current capacity. in this case, measures should be taken as described in section 13.3.7, boosting the lcd drive power supply. 357 v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 0 v 1 v 4 v 3 v ss seg 32 /cl 1 seg 31 /cl 2 seg 30 /do seg 29 /m h8/3867 series chip (a) 1/3 bias, 1/4 or 1/3 duty v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 0 v 1 v 4 v 3 v ss seg 32 /cl 1 seg 31 /cl 2 seg 30 /do seg 29 /m h8/3867 series chip (b) 1/2 duty v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 0 v 1 v 4 v 3 v ss seg 32 /cl 1 seg 31 /cl 2 seg 30 /do seg 29 /m h8/3867 series chip (c) static mode figure 13.18 connection to hd66100 358 359 section 14 power supply circuit 14.1 overview the h8/3867 series incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 1.5 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 1.8 v or above can be held down to virtually the same low level as when used at approximately 1.5 v. it is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit. 14.2 when using the internal power supply step-down circuit connect the external power supply to the v cc pin, and connect a capacitance of approximately 0.1 f between cv cc and v ss , as shown in figure 14.1. the internal step-down circuit is made effective simply by adding this external circuit. notes: 1. in the external circuit interface, the external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. 2. when the internal power supply step-down circuit is used, operating frequency f osc is 0.4 mhz to 2 mhz when v cc = 2.2 v to 5.5 v, and 0.4 mhz to 1 mhz otherwise. 3. the lcd power supply and a/d converter analog power supply are not affected by internal step-down processing. cv cc v ss internal logic step-down circuit internal power supply stabilization capacitance (approx. 0.1 f) v cc figure 14.1 power supply connection when internal step-down circuit is used 360 14.3 when not using the internal power supply step-down circuit when the internal power supply step-down circuit is not used, connect the external power supply to the v cc pin and cv cc pin, as shown in figure 14.2. the external power supply is then input directly to the internal power supply. note: the permissible range for the power supply voltage is 1.8 v to 5.5 v. operation cannot be guaranteed if a voltage outside this range (less than 1.8 v or more than 5.5 v) is input. cv cc v ss internal logic step-down circuit internal power supply v cc figure 14.2 power supply connection when internal step-down circuit is not used 361 section 15 electrical characteristics 15.1 h8/3867 series and h8/3827 series absolute maximum ratings table 15.1 lists the absolute maximum ratings. table 15.1 absolute maximum ratings item symbol value unit power supply voltage v cc , cv cc ?.3 to +7.0 v analog power supply voltage av cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.0 v input voltage ports other than port b v in ?.3 to v cc +0.3 v port b av in ?.3 to av cc +0.3 v operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 362 15.2 h8/3867 series and h8/3827 series electrical characteristics 15.2.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 1.8 3.0 5.5 v cc (v) f w (khz) all operating modes 32.768 4.5 6.0 2.0 3.2 4.0 0.4 1.0 1.8 2.2 3.0 2.6 4.5 5.5 v cc (v) v cc (v) fosc (mhz) fosc (mhz) active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit not used 1.0 2.0 0.4 1.8 2.2 5.5 active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit used 363 2. power supply voltage and operating frequency range 16.384 8.192 4.096 1.8 3.6 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 3.0 1.0 1.6 2.0 0.2 0.5 1.8 2.2 3.0 2.6 4.5 5.5 v cc (v) v cc (v) (mhz) (mhz) 375 125 200 250 4.096 62.5 1.8 2.2 3.0 2.6 4.5 5.5 v cc (v) (khz) 0.5 1.0 0.2 1.8 2.2 5.5 v cc (v) (khz) 62.5 125 4.096 1.8 2.2 5.5 active (medium-speed) mode (except a/d converter and pwm) sleep (medium-speed) mode (except a/d converter and pwm) internal power supply step-down circuit not used active (high-speed) mode sleep (high-speed) mode (except cpu) internal power supply step-down circuit not used active (high-speed) mode sleep (high-speed) mode (except cpu) internal power supply step-down circuit used active (medium-speed) mode (except a/d converter and pwm) sleep (medium-speed) mode (except a/d converter and pwm) internal power supply step-down circuit used subactive mode subsleep mode (except cpu) watch mode (except cpu) 364 3. analog power supply voltage and a/d converter operating range 250 200 1.8 3.0 5.5 av cc (v) (khz) 2.0 0.5 0.2 1.8 3.0 4.5 5.5 av cc (v) (mhz) 1.0 0.5 0.2 1.8 3.0 4.5 5.5 av cc (v) (mhz) 4.5 active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit not used active (medium-speed) mode sleep (medium-speed) mode internal power supply step-down circuit not used active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit used 365 15.2.2 dc characteristics table 15.2 lists the dc characteristics of the h8/3864. table 15.2 dc characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes input high v ih res , 0.8 v cc v cc + 0.3 v v cc = 4.0 to 5.5 v voltage wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg 0.9 v cc v cc + 0.3 except the above rxd 31 , rxd 32 , 0.7 v cc v cc + 0.3 v v cc = 4.0 to 5.5 v ud 0.8 v cc v cc + 0.3 except the above osc 1 0.8 v cc v cc + 0.3 v v cc = 4.0 to 5.5 v 0.9 v cc v cc + 0.3 except the above x 1 0.9 v cc v cc + 0.3 v v cc = 1.8 v to 5.5 v p1 0 to p1 7 , 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.8 v cc v cc + 0.3 except the above pb 0 to pb 7 0.7 v cc av cc + 0.3 v cc = 4.0 v to 5.5 v 0.8 v cc av cc + 0.3 except the above note: connect the test pin to v ss . 366 table 15.2 dc characteristics (cont) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes input low v il res , 0.3 0.2 v cc vv cc = 4.0 to 5.5 v voltage wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg 0.3 0.1 v cc except the above rxd 31 , rxd 32 , 0.3 0.3 v cc vv cc = 4.0 to 5.5 v ud 0.3 0.2 v cc except the above osc 1 0.3 0.2 when internal step- down circuit is used. 0.3 0.2 v cc vv cc = 4.0 to 5.5 v 0.3 0.1 v cc except the above x 1 0.3 0.1 v cc vv cc = 1.8 v to 5.5 v p1 0 to p1 7 , 0.3 0.3 v cc vv cc = 4.0 v to 5.5 v p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 0.3 0.2 v cc except the above output high voltage v oh p1 0 to p1 7 , p3 0 to p3 7 , v cc 1.0 vv cc = 4.0 v to 5.5 v i oh = 1.0 ma p4 0 to p4 2 , p5 0 to p5 7 , v cc 0.5 v cc = 4.0 v to 5.5 v i oh = 0.5 ma p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc 0.3 i oh = 0.1 ma 367 table 15.2 dc characteristics (cont) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes output low voltage v ol p1 0 to p1 7 , p4 0 to p4 2 0.6 v v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.5 i ol = 0.4 ma p3 0 to p3 7 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma input/output | i il | res , p4 3 20.0 a v in = 0.5 v to * 2 leakage 1.0 v cc 0.5 v * 1 current osc 1 , x 1 , p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 1.0 a v in = 0.5 v to v cc 0.5 v pb 0 to pb 7 1.0 v in = 0.5 v to av cc 0.5 v pull-up mos i p p1 0 to p1 7 , p3 0 to p3 7 , 50.0 300.0 a v cc = 5 v, v in = 0 v current p5 0 to p5 7 , p6 0 to p6 7 35.0 v cc = 2.7 v, v in = 0 v reference value 368 table 15.2 dc characteristics (cont) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes input capacitance c in all input pins except power supply, res , p4 3 , pb 0 to pb 7 15.0 pf f = 1 mhz, v in =0 v, t a = 25 c res 80.0 * 2 15.0 * 1 p4 3 50.0 * 2 15.0 * 1 pb 0 to pb 7 15.0 active mode current i ope1 v cc 0.7 1.0 ma active (high-speed) mode v cc = 5 v, f osc = 2mhz * 3 * 4 * 5 dissipation i ope2 v cc 0.3 0.5 ma active (medium- speed) mode v cc = 5 v, f osc = 2mhz divided by 128 * 3 * 4 * 5 sleep mode current dissipation i sleep v cc 0.4 0.6 ma v cc =5 v, f osc =2mhz * 3 * 4 * 5 subactive mode current dissipation i sub v cc 15 30 a v cc = 2.7 v, lcd on 32-khz crystal oscillator ( sub = w /2) * 3 * 4 * 5 8 a v cc = 2.7 v, lcd on 32-khz crystal oscillator ( sub = w /8) * 3 * 4 reference value * 5 subsleep mode current dissipation i subsp v cc 7.5 16 a v cc = 2.7 v, lcd on 32-khz crystal oscillator ( sub = w /2) * 3 * 4 * 5 369 table 15.2 dc characteristics (cont) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes watch mode current dissipation i watch v cc 2.8 6 a v cc = 2.7 v 3 2-khz crystal oscillator lcd not used * 3 * 4 * 5 standby mode current dissipation i stby v cc 1.0 5.0 a 32-khz crystal oscillator not used * 3 * 4 ram data retaining voltage v ram v cc 1.5 v * 3 * 4 notes: 1. applies to the mask rom products. 2. applies to the hd6473867 and hd6473827. 3. pin states during current measurement. mode res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc operates v cc halted system clock oscillator: crystal active (medium- speed) mode (i ope2 ) subclock oscillator: pin x 1 = gnd sleep mode v cc only timers operate v cc halted subactive mode v cc operates v cc halted system clock oscillator: subsleep mode v cc only timers operate, cpu stops v cc halted crystal subclock oscillator: watch mode v cc only time base operates, cpu stops v cc halted crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd 4. excludes current in pull-up mos transistors and output buffers. 5. when internal step-down circuit is used. 370 table 15.2 dc characteristics (cont) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes allowable output low i ol output pins except port 3 2.0 ma v cc = 4.0 v to 5.5 v current port 3 10.0 v cc = 4.0 v to 5.5 v (per pin) all output pins 0.5 allowable output low i ol output pins except port 3 40.0 ma v cc = 4.0 v to 5.5 v current port 3 80.0 v cc = 4.0 v to 5.5 v (total) all output pins 20.0 allowable i oh all output pins 2.0 ma v cc = 4.0 v to 5.5 v output high current (per pin) 0.2 except the above allowable i oh all output pins 15.0 ma v cc = 4.0 v to 5.5 v output high 10.0 except the above 371 15.2.3 ac characteristics table 15.3 lists the control signal timing, and tables 15.4 lists the serial interface timing of the h8/3864. table 15.3 control signal timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. applicable values reference item symbol pins min typ max unit test condition figure system clock f osc osc 1 , osc 2 0.4 6 mhz v cc = 4.5 v to 5.5 v * 2 oscillation 0.4 4v cc = 3.0 v to 5.5 v frequency 0.4 3.2 v cc = 2.6 v to 5.5 v 0.4 2v cc = 2.2 v to 5.5 v 0.4 1 except the above osc clock ( osc )t osc osc 1 , osc 2 167 2500 ns v cc = 4.5 v to 5.5 v figure 15.1 cycle time 250 2500 v cc = 3.0 v to 5.5 v * 2 313 2500 v cc = 2.6 v to 5.5 v 500 2500 v cc = 2.2 v to 5.5 v figure 15.1 1000 2500 except the above system clock ( )t cyc 2 128 t osc cycle time 244.1 s subclock oscillation frequency f w x 1 , x 2 32.768 or 38.4 khz watch clock ( w ) cycle time t w x 1 , x 2 30.5 or 26.0 s figure 15.1 subclock ( sub ) cycle time t subcyc 2 8t w * 1 instruction cycle time 2 t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 20 45 s figure 15.9 v cc = 2.2 v to 5.5 v figure 15.9 * 2 0.1 8 ms figure 15.9 v cc = 2.2 v to 5.5 v figure 15.9 50 ms except the above 372 table 15.3 control signal timing (cont) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. applicable values reference item symbol pins min typ max unit test condition figure oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high t cph osc 1 70 ns v cc = 4.5 v to 5.5 v figure 15.1 width 100 v cc = 3.0 v to 5.5 v * 2 140 v cc = 2.6 v to 5.5 v 200 v cc = 2.2 v to 5.5 v figure 15.1 400 except the above x 1 15.26 or 13.02 s external clock low t cpl osc 1 70 ns v cc = 4.5 v to 5.5 v figure 15.1 width 100 v cc = 3.0 v to 5.5 v * 2 140 v cc = 2.6 v to 5.5 v 200 v cc = 2.2 v to 5.5 v figure 15.1 400 except the above x 1 15.26 or 13.02 s external clock rise t cpr osc 1 20 ns v cc = 4.5 v to 5.5 v figure 15.1 time 30 v cc = 2.6 v to 5.5 v * 2 55 except the above figure 15.1 x 1 55.0 ns external clock fall t cpf osc 1 20 ns v cc = 4.5 v to 5.5 v figure 15.1 time 30 v cc = 2.6 v to 5.5 v * 2 55 except the above figure 15.1 x 1 55.0 ns pin res low width t rel res 10 t cyc figure 15.2 373 table 15.3 control signal timing (cont) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. applicable values reference item symbol pins min typ max unit test condition figure input pin high width t ih irq 0 to irq 4 , wkp 0 to wkp 7 adtrg , tmic tmif, tmig, aevl, aevh 2 t cyc t subcyc figure 15.3 input pin low width t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig, aevl, aevh 2 t cyc t subcyc figure 15.3 ud pin minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 15.4 notes: 1. selected with sa1 and sa0 of system clock control register 2 (syscr2). 2. internal power supply step-down circuit not used table 15.4 serial interface (sci3-1, sci3-2) timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values reference item symbol min typ max unit test conditions figure input clock asynchronous t scyc 4 t cyc or figure 15.5 cycle synchronous 6 t subcyc input clock pulse width t sckw 0.4 0.6 t scyc figure 15.5 transmit data delay time t txd 1t cyc or v cc = 4.0 v to 5.5 v figure 15.6 (synchronous) 1t subcyc except the above receive data setup time t rxs 200.0 ns v cc = 4.0 v to 5.5 v figure 15.6 * 1 (synchronous) 400.0 except the above figure 15.6 receive data hold time t rxh 200.0 ns v cc = 4.0 v to 5.5 v figure 15.6 * 1 (synchronous) 400.0 except the above figure 15.6 note: 1. when internal step-down circuit is not used. 374 15.2.4 a/d converter characteristics table 15.5 shows the a/d converter characteristics of the h8/3864. table 15.5 a/d converter characteristics v cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. applicable values reference item symbol pins min typ max unit test condition figure analog power supply voltage av cc av cc 1.8 5.5 v * 1 analog input voltage av in an 0 to an 7 0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5 v supply current ai stop1 av cc 600 a * 2 reference value ai stop2 av cc 5a * 3 analog input capacitance c ain an 0 to an 7 15.0 pf allowable signal source impedance r ain 10.0 k resolution (data length) 10 bit nonlinearity error 2.5 lsb av cc = 3.0 v to 5.5 v v cc = 3.0 v to 5.5 v * 4 5.5 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v 7.5 except the above * 5 quantization error 0.5 lsb 375 table 15.5 a/d converter characteristics (cont) v cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. applicable values reference item symbol pins min typ max unit test condition figure absolute accuracy 3.0 lsb av cc = 3.0 v to 5.5 v v cc = 3.0 v to 5.5 v * 4 6.0 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v 8.0 except the above * 5 conversion time 15.5 155 s av cc = 3.0 v to 5.5 v v cc = 3.0 v to 5.5 v * 4 62 155 except the above notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. when internal step-down circuit is not used. 5. conversion time 124 s 376 15.2.5 lcd characteristics table 15.6 shows the lcd characteristics. table 15.6 lcd characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise specified. applicable test values reference item symbol pins conditions min typ max unit figure segment driver drop voltage v ds seg 1 to seg 32 i d = 2 a v 1 = 2.7 to 5.5 v 0.6 v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 a v 1 = 2.7 to 5.5 v 0.3 v * 1 lcd power supply split-resistance r lcd between v 1 and v ss 0.5 3.0 9.0 m on-chip liquid crystal display power supply voltage v lp v 0 5.0 v * 2 reference value liquid crystal display voltage v lcd v 1 2.2 5.5 v * 3 notes: 1. the voltage drop from power supply pins v 1 , v 2 , v 3 , and vss to each segment pin or common pin. 2. the output voltage in step-up constant-voltage power supply operation (unloaded). 3. when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v 1 v 2 v 3 v ss . 377 table 15.7 ac characteristics for external segment expansion v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise specified. applicable test values reference item symbol pins conditions min typ max unit figure clock high width t cwh cl 1 , cl 2 * 1 800 ns figure 15.9 clock low width t cwl cl 2 * 1 800 ns figure 15.9 clock setup time t csu cl 1 , cl 2 * 1 500 ns figure 15.9 data setup time t su do * 1 300 ns figure 15.9 data hold time t dh do * 1 300 ns figure 15.9 m delay time t dm m 1000 1000 ns figure 15.9 clock rise and fall times t ct cl 1 , cl 2 170 ns figure 15.9 note: 1. value when the frame frequency is set to between 30.5 hz and 488 hz. 378 15.3 operation timing figures 15.1 to 15.6 show timing diagrams. t , tw osc v ih v il t cph t cpl t cpr o sc1 x 1 t cpf figure 15.1 clock input timing res v il t rel figure 15.2 res low width v ih v il t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig, aevl, aevh t ih figure 15.3 input timing 379 t udl v ih v il t udh ud figure 15.4 ud pin minimum modulation width timing t scyc 31 t sckw sck 32 sck figure 15.5 sck3 input clock timing 380 32 t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol oh ol sck 31 sck txd 31 txd 32 (transmit data) rxd 31 rxd 32 (receive data) note: * output timing reference levels output high output low load conditions are shown in figure 15-8. v = 1/2vcc + 0.2 v v = 0.8 v figure 15.6 sci3 synchronous mode input/output timing 381 cl 1 cl 2 do m t su t ct t dh t cwl t cwh t cwh t csu t ct t csu t dm v cc 0.5v v cc 0.5v 0.4v 0.4v 0.4v v cc 0.5v 0.4v figure 15.7 segment expansion signal timing 382 15.4 output load circuit v cc 2.4 k ? 12 k ? 30 pf output pin figure 15.8 output load condition 15.5 resonator equivalent circuit c s c o frequency (mhz) r s (max) c o (max) 1 40 ? 3.5 pf 4.193 100 ? 16 pf r s (max) c o (max) 0.4 8.6 ? 326 pf 4 8.8 ? 36 pf crystal resonator parameter r s osc 2 osc 1 l s frequency (mhz) ceramic resonator parameters figure 15.9 resonator equivalent circuit 383 appendix a cpu instruction set a.1 instructions operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition subtraction multiplication division logical and logical or exclusive logical or move logical complement condition code notation symbol modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 not affected by the instruction execution result 384 table a.1 lists the h8/300l cpu instruction set. table a.1 instruction set mnemonic operation i h n z v c mov.b #xx:8, rd b #xx:8 rd8 2 ?? 0 2 mov.b rs, rd b rs8 rd8 2 ?? 0 2 mov.b @rs, rd b @rs16 rd8 2 ?? 0 4 mov.b @(d:16, rs), rd b @(d:16, rs16) rd8 4 ?? 0 6 mov.b @rs+, rd b @rs16 rd8 2 ?? 0 6 rs16+1 rs16 mov.b @aa:8, rd b @aa:8 rd8 2 ?? 0 4 mov.b @aa:16, rd b @aa:16 rd8 4 ?? 0 6 mov.b rs, @rd b rs8 @rd16 2 ?? 0 4 mov.b rs, @(d:16, rd) b rs8 @(d:16, rd16) 4 ?? 0 6 mov.b rs, @ rd b rd16 1 rd16 2 ?? 0 6 rs8 @rd16 mov.b rs, @aa:8 b rs8 @aa:8 2 ?? 0 4 mov.b rs, @aa:16 b rs8 @aa:16 4 ?? 0 6 mov.w #xx:16, rd w #xx:16 rd 4 ?? 0 4 mov.w rs, rd w rs16 rd16 2 ?? 0 2 mov.w @rs, rd w @rs16 rd16 2 ?? 0 4 mov.w @(d:16, rs), rd w @(d:16, rs16) rd16 4 ?? 0 6 mov.w @rs+, rd w @rs16 rd16 2 ?? 0 6 rs16+2 rs16 mov.w @aa:16, rd w @aa:16 rd16 4 ?? 0 6 mov.w rs, @rd w rs16 @rd16 2 ?? 0 4 mov.w rs, @(d:16, rd) w rs16 @(d:16, rd16) 4 ?? 0 6 mov.w rs, @ rd w rd16 2 rd16 2 ?? 0 6 rs16 @rd16 mov.w rs, @aa:16 w rs16 @aa:16 4 ?? 0 6 pop rd w @sp rd16 2 ?? 0 6 sp+2 sp push rs w sp 2 sp 2 ?? 0 6 rs16 @sp #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size 385 table a.1 instruction set (cont) mnemonic operation i h n z v c add.b #xx:8, rd b rd8+#xx:8 rd8 2 ????? 2 add.b rs, rd b rd8+rs8 rd8 2 ????? 2 add.w rs, rd w rd16+rs16 rd16 2 (1) ???? 2 addx.b #xx:8, rd b rd8+#xx:8 +c rd8 2 ?? (2) ?? 2 addx.b rs, rd b rd8+rs8 +c rd8 2 ?? (2) ?? 2 adds.w #1, rd w rd16+1 rd16 2 2 adds.w #2, rd w rd16+2 rd16 2 2 inc.b rd b rd8+1 rd8 2 ??? 2 daa.b rd b rd8 decimal adjust rd8 2 * ?? * (3) 2 sub.b rs, rd b rd8 rs8 rd8 2 ????? 2 sub.w rs, rd w rd16 rs16 rd16 2 (1) ???? 2 subx.b #xx:8, rd b rd8 #xx:8 c rd8 2 ?? (2) ?? 2 subx.b rs, rd b rd8 rs8 c rd8 2 ?? (2) ?? 2 subs.w #1, rd w rd16 1 rd16 2 2 subs.w #2, rd w rd16 2 rd16 2 2 dec.b rd b rd8 1 rd8 2 ??? 2 das.b rd b rd8 decimal adjust rd8 2 * ?? * 2 neg.b rd b 0 rd rd 2 ????? 2 cmp.b #xx:8, rd b rd8 #xx:8 2 ????? 2 cmp.b rs, rd b rd8 rs8 2 ????? 2 cmp.w rs, rd w rd16 rs16 2 (1) ???? 2 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size 386 table a.1 instruction set (cont) mnemonic operation i h n z v c mulxu.b rs, rd b rd8 rs8 rd16 2 14 divxu.b rs, rd b rd16 rs8 rd16 2 (5) (6) 14 (rdh: remainder, rdl: quotient) and.b #xx:8, rd b rd8 #xx:8 rd8 2 ?? 0 2 and.b rs, rd b rd8 rs8 rd8 2 ?? 0 2 or.b #xx:8, rd b rd8 #xx:8 rd8 2 ?? 0 2 or.b rs, rd b rd8 rs8 rd8 2 ?? 0 2 xor.b #xx:8, rd b rd8 #xx:8 rd8 2 ?? 0 2 xor.b rs, rd b rd8 rs8 rd8 2 ?? 0 2 not.b rd b rd rd 2 ?? 0 2 shal.b rd b 2 ???? 2 shar.b rd b 2 ?? 0 ? 2 shll.b rd b 2 ?? 0 ? 2 shlr.b rd b 2 0 ? 0 ? 2 rotxl.b rd b 2 ?? 0 ? 2 rotxr.b rd b 2 ?? 0 ? 2 b 7 b 0 0 c c b 7 b 0 b 7 b 0 0 c b 7 b 0 0c c b 7 b 0 c b 7 b 0 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size 387 table a.1 instruction set (cont) mnemonic operation i h n z v c rotl.b rd b 2 ?? 0 ? 2 rotr.b rd b 2 ?? 0 ? 2 bset #xx:3, rd b (#xx:3 of rd8) 12 2 bset #xx:3, @rd b (#xx:3 of @rd16) 14 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) 14 8 bset rn, rd b (rn8 of rd8) 12 2 bset rn, @rd b (rn8 of @rd16) 14 8 bset rn, @aa:8 b (rn8 of @aa:8) 14 8 bclr #xx:3, rd b (#xx:3 of rd8) 02 2 bclr #xx:3, @rd b (#xx:3 of @rd16) 04 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) 04 8 bclr rn, rd b (rn8 of rd8) 02 2 bclr rn, @rd b (rn8 of @rd16) 04 8 bclr rn, @aa:8 b (rn8 of @aa:8) 04 8 bnot #xx:3, rd b (#xx:3 of rd8) 2 2 ( #xx:3 of rd8 ) bnot #xx:3, @rd b (#xx:3 of @rd16) 4 8 ( #xx:3 of @rd16 ) bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) 4 8 ( #xx:3 of @aa:8 ) bnot rn, rd b (rn8 of rd8) 2 2 ( rn8 of rd8 ) bnot rn, @rd b (rn8 of @rd16) 4 8 ( rn8 of @rd16 ) bnot rn, @aa:8 b (rn8 of @aa:8) 4 8 ( rn8 of @aa:8 ) #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size c b 7 b 0 c b 7 b 0 388 table a.1 instruction set (cont) mnemonic operation i h n z v c btst #xx:3, rd b ( #xx:3 of rd8 ) z2 ? 2 btst #xx:3, @rd b ( #xx:3 of @rd16 ) z4 ? 6 btst #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) z4 ? 6 btst rn, rd b ( rn8 of rd8 ) z2 ? 2 btst rn, @rd b ( rn8 of @rd16 ) z4 ? 6 btst rn, @aa:8 b ( rn8 of @aa:8 ) z4 ? 6 bld #xx:3, rd b (#xx:3 of rd8) c2 ? 2 bld #xx:3, @rd b (#xx:3 of @rd16) c4 ? 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) c4 ? 6 bild #xx:3, rd b ( #xx:3 of rd8 ) c2 ? 2 bild #xx:3, @rd b ( #xx:3 of @rd16 ) c4 ? 6 bild #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) c4 ? 6 bst #xx:3, rd b c (#xx:3 of rd8) 2 2 bst #xx:3, @rd b c (#xx:3 of @rd16) 4 8 bst #xx:3, @aa:8 b c (#xx:3 of @aa:8) 4 8 bist #xx:3, rd b c (#xx:3 of rd8) 2 2 bist #xx:3, @rd b c (#xx:3 of @rd16) 4 8 bist #xx:3, @aa:8 b c (#xx:3 of @aa:8) 4 8 band #xx:3, rd b c (#xx:3 of rd8) c2 ? 2 band #xx:3, @rd b c (#xx:3 of @rd16) c4 ? 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 ? 6 biand #xx:3, rd b c ( #xx:3 of rd8 ) c2 ? 2 biand #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 ? 6 biand #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 ? 6 bor #xx:3, rd b c (#xx:3 of rd8) c2 ? 2 bor #xx:3, @rd b c (#xx:3 of @rd16) c4 ? 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 ? 6 bior #xx:3, rd b c ( #xx:3 of rd8 ) c2 ? 2 bior #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 ? 6 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size 389 table a.1 instruction set (cont) mnemonic operation i h n z v c bior #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 ? 6 bxor #xx:3, rd b c (#xx:3 of rd8) c2 ? 2 bxor #xx:3, @rd b c (#xx:3 of @rd16) c4 ? 6 bxor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 ? 6 bixor #xx:3, rd b c ( #xx:3 of rd8 ) c2 ? 2 bixor #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 ? 6 bixor #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 ? 6 bra d:8 (bt d:8) pc pc+d:8 2 4 brn d:8 (bf d:8) pc pc+2 2 4 bhi d:8 c z = 0 2 4 bls d:8 c z = 1 2 4 bcc d:8 (bhs d:8) c = 0 2 4 bcs d:8 (blo d:8) c = 1 2 4 bne d:8 z = 0 2 4 beq d:8 z = 1 2 4 bvc d:8 v = 0 2 4 bvs d:8 v = 1 2 4 bpl d:8 n = 0 2 4 bmi d:8 n = 1 2 4 bge d:8 n v = 0 2 4 blt d:8 n v = 1 2 4 bgt d:8 z (n v) = 0 2 4 ble d:8 z (n v) = 1 2 4 jmp @rn pc rn16 2 4 jmp @aa:16 pc aa:16 4 6 jmp @@aa:8 pc @aa:8 2 8 bsr d:8 sp 2 sp 2 6 pc @sp pc pc+d:8 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size if condition is true then pc pc+d:8 else next; branching condition 390 table a.1 instruction set (cont) mnemonic operation i h n z v c jsr @rn sp 2 sp 2 6 pc @sp pc rn16 jsr @aa:16 sp 2 sp 4 8 pc @sp pc aa:16 jsr @@aa:8 sp 2 sp 2 8 pc @sp pc @aa:8 rts pc @sp 2 8 sp+2 sp rte ccr @sp 2 ?????? 10 sp+2 sp pc @sp sp+2 sp sleep transit to sleep mode. 2 2 ldc #xx:8, ccr b #xx:8 ccr 2 ?????? 2 ldc rs, ccr b rs8 ccr 2 ?????? 2 stc ccr, rd b ccr rd8 2 2 andc #xx:8, ccr b ccr #xx:8 ccr 2 ?????? 2 orc #xx:8, ccr b ccr #xx:8 ccr 2 ?????? 2 xorc #xx:8, ccr b ccr #xx:8 ccr 2 ?????? 2 nop pc pc+2 2 2 eepmov if r4l 04 (4) repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l 1 r4l until r4l=0 else next; notes: (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) the number of states required for execution is 4n + 9 (n = value of r4l). (5) set to 1 if the divisor is negative; otherwise cleared to 0. (6) set to 1 if the divisor is zero; otherwise cleared to 0. #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size 391 a.2 operation code map table a.2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 392 high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * note: bit-manipulation instructions the push and pop instructions are identical in machine language to mov instructions. * table a.2 operation code map 393 a.3 number of execution states the tables here can be used to calculate the number of states required for instruction execution. table a.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table a.3 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 394 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m internal operation s n 1 note: * depends on which on-chip module is accessed. see 2.9.1, notes on data access for details. 395 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1, rd 1 adds.w #2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 396 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 397 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp. b #xx:8, rd 1 cmp. b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16, rs), rd 2 1 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 2 1 mov.b rs, @ rd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 2 1 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 note: n: initial value in r4l. the source and destination operands are accessed n + 1 times each. 398 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 2 1 mov.w rs, @ rd 1 1 2 mov.w rs, @aa:16 2 1 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1, rd 1 subs.w #2, rd 1 pop pop rd 1 1 2 push push rs 1 1 2 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 399 appendix b internal i/o registers b.1 addresses lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'90 wegr wkegs7 wkegs6 wkegs5 wkegs4 wkegs3 wkegs2 wkegs1 wkegs0 system control h'91 spcr spc32 spc31 scinv3 scinv2 scinv1 scinv0 sci h'92 cwosr cwos timer a h'93 h'94 h'95 eccsr ovh ovl ch2 cueh cuel crch crcl asynchro- h'96 ech ech7 ech6 ech5 ech4 ech3 ech2 ech1 ech0 nous event h'97 ecl ecl7 ecl6 ecl5 ecl4 ecl3 ecl2 ecl1 ecl0 counter h'98 smr31 com31 chr31 pe31 pm31 stop31 mp31 cks311 cks310 sci31 h'99 brr31 brr317 brr316 brr315 brr314 brr313 brr312 brr311 brr310 h'9a scr31 tie31 rie31 te31 re31 mpie31 teie31 cke31 cke310 h'9b tdr31 tdr317 tdr316 tdr315 tdr314 tdr313 tdr312 tdr311 tdr310 h'9c ssr31 tdre31 rdrf31 oer31 fer31 per31 tend31 mpbr31 mpbt31 h'9d rdr31 rdr317 rdr316 rdr315 rdr314 rdr313 rdr312 rdr311 rdr310 h'9e h'9f h'a0 h'a1 h'a2 h'a3 h'a4 h'a5 h'a6 h'a7 h'a8 smr32 com32 chr32 pe32 pm32 stop32 mp32 cks321 cks320 sci32 h'a9 brr32 brr327 brr326 brr325 brr324 br323 brr322 brr321 brr320 h'aa scr32 tie32 rie32 te32 re32 mpie32 teie32 cke321 cke320 h'ab tdr32 tdr327 tdr326 tdr325 tdr324 tdr323 tdr322 tdr321 tdr320 h'ac ssr32 tdre32 rdrf32 oer32 fer32 per32 tend32 mpbr32 mpbt32 h'ad rdr32 rdr327 rdr326 rdr325 rdr324 rdr323 rdr322 rdr321 rdr320 h'ae h'af h'b0 tma tma7 tma6 tma5 tma3 tma2 tma1 tma0 timer a 400 lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'b1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 timer a h'b2 tcsrw b6wi tcwe b4wi tcsrwe b2wi wdon bow1 wrst watchdog h'b3 tcw tcw7 tcw6 tcw5 tcw4 tcw3 tcw2 tcw1 tcwo timer h'b4 tmc tmc7 tmc6 tmc5 tmc2 tmc1 tmc0 timer c h'b5 tcc/tlc tcc/ tlc7 tcc6/ tlc6 tcc5/ tlc5 tcc4/ tlc4 tcc3/ tlc3 tcc2/ tlc2 tcc1/ tlc1 tcc0/ tlc0 h'b6 tcrf tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 timer f h'b7 tcsrf ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl h'b8 tcfh tcfh7 tcfh6 tcfh5 tcfh4 tcfh3 tcfh2 tcfh1 tcfh0 h'b9 tcfl tcfl7 tcfl6 tcfl5 tcfl4 tcfl3 tcfl2 tcfl1 tcfl0 h'ba ocrfh ocrfh7 ocrfh6 ocrfh5 ocrfh4 ocrfh3 ocrfh2 ocrfh1 ocrfh0 h'bb ocrfl ocrfl7 ocrfl6 ocrfl5 ocrfl4 ocrfl3 ocrfl2 ocrfl1 ocrfl0 h'bc tmg ovfh ovfl ovie iiegs cclr1 cclr0 cks1 cks0 timer g h'bd icrgf icrgf7 icrgf6 icrgf5 icrgf4 icrgf3 icrgf2 icrgf1 icrgfo h'be icrgr icrgr7 icrgr6 icrgr5 icrgr4 icrgr3 icrgr2 icrgr1 icrgro h'bf h'c0 lpcr dts1 dts0 cmx sgx sgs3 sgs2 sgs1 sgs0 lcd h'c1 lcr psw act disp cks3 cks2 cks1 cks0 controller/ h'c2 lcr2 lcdab sups cds3 cds2 cds1 cds0 driver h'c3 h'c4 adrrh adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 a/d h'c5 adrrl adr1 adr0 converter h'c6 amr cks trge ch3 ch2 ch1 ch0 h'c7 adsr adsf h'c8 pmr1 irq3 irq2 irq1 irq4 tmig tmofh tmofl tmow i/o port h'c9 h'ca pmr3 aevl aevh wdcks ncs irq0 reso ud pwm h'cb h'cc pmr5 wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 h'cd h'ce h'cf h'd0 pwcr pwcr1 pwcr0 bit 14 h'd1 pwdru pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 pwm h'd2 pwdrl pwdrl7 pwdrl6 pwdrl5 pwdrl4 pwdrl3 pwdrl2 pwdrl1 pwdrl0 h'd3 h'd4 pdr1 p17 p16 p15 p14 p13 p12 p11 p10 i/o port 401 lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'd5 i/o port h'd6 pdr3 p37 p36 p35 p34 p33 p32 p31 p30 h'd7 pdr4 p43p42p41p40 h'd8 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 h'd9 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 h'da pdr7 p77 p76 p75 p74 p73 p72 p71 p70 h'db pdr8 p87 p86 p85 p84 p83 p82 p81 p80 h'dc h'dd pdra pa3pa2pa1pa0 h'de pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'df h'e0 pucr1 pucr17 pucr16 pucr15 pucr14 pucr13 pucr12 pucr11 pucr10 i/o port h'e1 pucr3 pucr37 pucr36 pucr35 pucr34 pucr33 pucr32 pucr31 pucr30 h'e2 pucr5 pucr57 pucr56 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 h'e3 pucr6 pucr67 pucr66 pucr65 pucr64 pucr63 pucr62 pucr61 pucr60 h'e4 pcr1 pcr17 pcr16 pcr15 pcr14 pcr13 pcr12 pcr11 pcr10 h'e5 h'e6 pcr3 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 h'e7 pcr4 pcr42 pcr41 pcr40 h'e8 pcr5 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 h'e9 pcr6 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 h'ea pcr7 pcr77 pcr76 pcr75 pcr74 pcr73 pcr72 pcr71 pcr70 h'eb pcr8 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 h'ec h'ed pcra pcra3 pcra2 pcra1 pcra0 h'ee h'ef h'f0 syscr1 ssby sts2 sts1 sts0 lson ma1 ma0 system h'f1 syscr2 nesel dton mson sa1 sa0 control h'f2 iegr ieg4 ieg3 ieg2 ieg1 ieg0 h'f3 ienr1 ienta ienwp ien4 ien3 ien2 ien1 ien0 h'f4 ienr2 iendt ienad ientg ientfh ientfl ientc ienec h'f5 h'f6 irr1 irrta irri4 irri3 irri2 irri1 irri0 h'f7 irri2 irrdt irrad irrtg irrtfh irrtfl irrtc irrec h'f8 402 lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'f9 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 system h'fa ckstpr1 s31ckstp s32ckstp adckstp tgckstp tfckstp tcckstp tackstp control h'fb ckstpr2 aeckstp wdckstp pwckstp ldckstp h'fc h'fd h'fe h'ff legend sci: serial communication interface 403 b.2 functions tmc?imer mode register c h'b4 timer c register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes ( ) indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 1 clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 10 1 1 00 1 10 1 internal clock: internal clock: internal clock: external event (tmic): /8192 /2048 /512 /64 /16 /4 /4 rising or falling edge w counter up/down control tcc is an up-counter tcc is a down-counter 0 0 1 tcc up/down control is determined by input at pin ud. tcc is a down-counter if the ud input is high, and an up-counter if the ud input is low. 1 * auto-reload function select interval timer function selected * : don t care auto-reload function selected 0 1 404 wegr?akeup edge select register h'90 system control b it i nitial value r ead/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w 4 wkegs4 0 r/w wkpn edge selected 0 wkpn pin falling edge detected (n = 0 to 7) 1 wkpn pin rising edge detected 3 wkegs3 0 r/w 405 spcr?erial port control register h'91 sci b it i nitial value r ead/write 7 1 6 1 5 spc32 0 r/w 0 scinv0 0 r/w 2 scinv2 0 r/w 1 scinv1 0 r/w 4 spc31 0 r/w rxd 31 pin input data inversion switch 0 rxd 31 input data is not inverted 1 rxd 31 input data is inverted txd 31 pin output data inversion switch 0 txd 31 output data is not inverted 1 txd 31 output data is inverted rxd 32 pin input data inversion switch 0 rxd 32 input data is not inverted 1 rxd 32 input data is inverted txd 32 pin output data inversion switch 0 txd 32 output data is not inverted 1 txd 32 output data is inverted p3 5 txd 31 pin function switch 0 functions as p3 5 i/o pin 1 functions as txd 31 output pin p4 2 /txd 32 pin function switch 0 function as p4 2 i/o pin 1 function as txd 32 output pin 3 scinv3 0 r/w 406 cwosr?ubclock output select register h'92 timer a b it i nitial value r ead/write 7 1 r 6 1 r 5 1 r 0 cwos 0 r/w 2 1 r 1 1 r 4 1 r tmow pin clock select 0 clock output from tma is output 1 w is output 3 1 r 407 eccsr?vent counter control/status register h'95 aec b it i nitial value r ead/write 7 ovh 0 r/w 6 ovl 0 r/w 5 0 r/w 0 crcl 0 r/w 2 cuel 0 r/w 1 crch 0 r/w 4 ch2 0 r/w counter reset control l 0 1 ecl is reset ecl reset is cleared and count-up function is enabled counter reset control h 0 ech is reset 1 ech reset is cleared and count-up function is enabled count-up enable l 0 ecl event clock input is disabled. ecl value is held 1 ecl event clock input is enabled count-up enable h 0 ech event clock input is disabled. ech value is held 1 ech event clock input is enabled channel select 0 ech and ecl are used together as a single- channel 16-bit event counter 1 ech and ecl are used as two independent 8-bit event counter channels counter overflow l 0 ecl has not overflowed 1 ecl has overflowed counter overflow h 0 ech has not overflowed 1 ech has overflowed 3 cueh 0 r/w 408 ech?vent counter h h'96 aec b it i nitial value r ead/write 7 ech7 0 r 6 ech6 0 r 5 ech5 0 r 0 ech0 0 r 2 ech2 0 r 1 ech1 0 r 4 ech4 0 r 3 ech3 0 r ecl?vent counter l h'97 aec b it i nitial value r ead/write 7 ecl7 0 r 6 ecl6 0 r 5 ecl5 0 r 0 ecl0 0 r 2 ecl2 0 r 1 ecl1 0 r 4 ecl4 0 r 3 ecl3 0 r 409 smr31?erial mode register 31 h'98 sci31 b it i nitial value r ead/write 7 com31 0 r/w 6 chr31 0 r/w 5 pe31 0 r/w 0 cks310 0 r/w 2 mp31 0 r/w 1 cks311 0 r/w 4 pm31 0 r/w clock select 0 0 01 1 1 1 clock w/2 clock 0 /16 clock /64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity parity enable 0 parity bit addition and checking disabled 1 parity bit addition and checking enabled character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data communication mode 0 asynchronous mode 1 synchronous mode 3 stop31 0 r/w 410 brr31?it rate register31 h'99 sci31 bit initial value read/write 7 brr317 1 r/w 6 brr316 1 r/w 5 brr315 1 r/w 4 brr314 1 r/w 3 brr313 1 r/w 0 brr310 1 r/w 2 brr312 1 r/w 1 brr311 1 r/w 411 scr31?erial control register 31 h'9a sci31 b it i nitial value r ead/write 7 tie31 0 r/w 6 rie31 0 r/w 5 te31 0 r/w 0 cke310 0 r/w 2 teie31 0 r/w 1 cke311 0 r/w 4 re31 0 r/w receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (normal receive operation) [clearing conditions] when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled the receive interrupt request (rxi), receive error interrupt request (eri), and setting of the rdrf, fer, and oer flags in the serial status register (ssr), are disabled until data with the multiprocessor bit set to 1 is received. transmit enable 0 transmit operation disabled (txd pin is transmit data pin) 1 transmit operation enabled (txd pin is transmit data pin) receive enable 0 receive operation disabled (rxd pin is i/o port) 1 receive operation enabled (rxd pin is receive data pin) transmit end interrupt enable clock enable 0 bit 1 cke311 0 0 1 1 bit 0 cke310 0 1 0 1 communication mode asynchronous synchronous asynchronous synchronous asynchronous synchronous asynchronous synchronous internal clock internal clock internal clock reserved (do not specify this combination) external clock external clock reserved (do not specify this combination) reserved (do not specify this combination) i/o port serial clock output clock output clock input serial clock input clock source sck pin function description transmit end interrupt request (tei) disabled 1 transmit end interrupt request (tei) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled 3 mpie31 0 r/w 3 412 tdr31?ransmit data register 31 h'9b sci31 bit initial value read/write 7 tdr317 1 r/w 6 tdr316 1 r/w 5 tdr315 1 r/w 4 tdr314 1 r/w 3 tdr313 1 r/w 0 tdr310 1 r/w 2 tdr312 1 r/w 1 tdr311 1 r/w data for transfer to tsr 413 ssr31?erial status register31 h'9c sci3 b it i nitial value r ead/write n ote: * only a write of 0 for flag clearing is possible. 7 tdre31 1 r/(w) 6 rdrf31 0 r/(w) 5 oer31 0 r/(w) 0 mpbt31 0 r/w 2 tend31 1 r 1 mpbr31 0 r 4 fer31 0 r/(w) receive data register full 0 there is no receive data in rdr31 [clearing conditions] after reading rdrf31 = 1, cleared by writing 0 to rdrf31 when rdr31 data is read by an instruction 1 there is receive data in rdr31 [setting conditions] when reception ends normally and receive data is transferred from rsr31 to rdr31 transmit data register empty 0 transmit data written in tdr31 has not been transferred to tsr31 [clearing conditions] after reading tdre31 = 1, cleared by writing 0 to tdre31 when data is written to tdr31 by an instruction 1 transmit data has not been written to tdr31, or transmit data written in tdr31 has been transferred to tsr31 [setting conditions] when bit te in serial control register 31 (scr31) is cleared to 0 when data is transferred from tdr31 to tsr31 transmit end 0 transmission in progress [clearing conditions] 1 transmission ended [setting conditions] parity error 0 reception in progress or completed normally [clearing conditions] after reading per31 = 1, cleared by writing 0 to per31 1 a parity error has occurred during reception [setting conditions] framing error 0 reception in progress or completed normally [clearing conditions] after reading fer31 = 1, cleared by writing 0 to fer31 1 a framing error has occurred during reception [setting conditions] when the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 overrun error 0 reception in progress or completed [clearing conditions] after reading oer31 = 1, cleared by writing 0 to oer31 1 an overrun error has occurred during reception [setting conditions] when the next serial reception is completed with rdrf31 set to 1 multiprocessor bit receive multiprocessor bit transfer 0 data in which the multiprocessor bit is 0 has been received 1 data in which the multiprocessor bit is 1 has been received 0 a 0 multiprocessor bit is transmitted 1 a 1 multiprocessor bit is transmitted 3 per31 0 r/(w) ***** after reading tdre31 = 1, cleared by writing 0 to tdre when data is written to tdr31 by an instruction when bit te in serial control register 31 (scr31) is cleared to 0 when bit tdre31 is set to 1 when the last bit of a transmit character is sent when the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (pm31) in the serial mode register (smr31) 414 rdr31?eceive data register 31 h'f9d sci31 bit initial value read/write 7 rdr317 0 r 6 rdr316 0 r 5 rdr315 0 r 4 rdr314 0 r 3 rdr313 0 r 0 rdr310 0 r 2 rdr312 0 r 1 rdr311 0 r 415 smr32?erial mode register 32 h'a8 sci32 b it i nitial value r ead/write 7 com32 0 r/w 6 chr32 0 r/w 5 pe32 0 r/w 0 cks320 0 r/w 2 mp32 0 r/w 1 cks321 0 r/w 4 pm32 0 r/w clock select 0 0 01 1 1 1 clock w/2 clock 0 /16 clock /64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity parity enable 0 parity bit addition and checking disabled 1 parity bit addition and checking enabled character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data communication mode 0 asynchronous mode 1 synchronous mode 3 stop32 0 r/w 416 brr32?it rate register 32 h'a9 sci32 bit initial value read/write 7 brr327 1 r/w 6 brr326 1 r/w 5 brr325 1 r/w 4 brr324 1 r/w 3 brr323 1 r/w 0 brr3120 1 r/w 2 brr322 1 r/w 1 brr321 1 r/w 417 scr32?erial control register 32 h'aa sci32 b it i nitial value r ead/write 7 tie32 0 r/w 6 rie32 0 r/w 5 te32 0 r/w 0 cke320 0 r/w 2 teie32 0 r/w 1 cke321 0 r/w 4 re32 0 r/w receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (normal receive operation) [clearing conditions] when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled the receive interrupt request (rxi), receive error interrupt request (eri), and setting of the rdrf, fer, and oer flags in the serial status register (ssr), are disabled until data with the multiprocessor bit set to 1 is received. transmit enable 0 transmit operation disabled (txd pin is transmit data pin) 1 transmit operation enabled (txd pin is transmit data pin) receive enable 0 receive operation disabled (rxd pin is i/o port) 1 receive operation enabled (rxd pin is receive data pin) transmit end interrupt enable clock enable 0 bit 1 cke321 0 0 1 1 bit 0 cke320 0 1 0 1 communication mode asynchronous synchronous asynchronous synchronous asynchronous synchronous asynchronous synchronous internal clock internal clock internal clock reserved (do not specify this combination) external clock external clock reserved (do not specify this combination) reserved (do not specify this combination) i/o port serial clock output clock output clock input serial clock input clock source sck pin function description transmit end interrupt request (tei) disabled 1 transmit end interrupt request (tei) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled 3 mpie32 0 r/w 3 418 tdr32?ransmit data register 32 h'ab sci32 bit initial value read/write 7 tdr327 1 r/w 6 tdr326 1 r/w 5 tdr325 1 r/w 4 tdr324 1 r/w 3 tdr323 1 r/w 0 tdr320 1 r/w 2 tdr322 1 r/w 1 tdr321 1 r/w data for transfer to tsr 419 ssr32?erial status register 32 h'ac sci32 b it i nitial value r ead/write n ote: * only a write of 0 for flag clearing is possible. 7 tdre32 1 r/(w) 6 rdrf32 0 r/(w) 5 oer32 0 r/(w) 0 mpbt32 0 r/w 2 tend32 1 r 1 mpbr32 0 r 4 fer32 0 r/(w) receive data register full 0 there is no receive data in rdr32 [clearing conditions] after reading rdrf32 = 1, cleared by writing 0 to rdrf32 when rdr32 data is read by an instruction 1 there is receive data in rdr32 [setting conditions] when reception ends normally and receive data is transferred from rsr32 to rdr32 transmit data register empty 0 transmit data written in tdr32 has not been transferred to tsr32 [clearing conditions] after reading tdre32 = 1, cleared by writing 0 to tdre32 when data is written to tdr32 by an instruction 1 transmit data has not been written to tdr32, or transmit data written in tdr32 has been transferred to tsr32 [setting conditions] when bit te32 in serial control register 32 (scr32) is cleared to 0 when data is transferred from tdr32 to tsr32 transmit end 0 transmission in progress [clearing conditions] 1 transmission ended [setting conditions] parity error 0 reception in progress or completed normally [clearing conditions] after reading per32 = 1, cleared by writing 0 to per32 1 a parity error has occurred during reception [setting conditions] framing error 0 reception in progress or completed normally [clearing conditions] after reading fer32 = 1, cleared by writing 0 to fer32 1 a framing error has occurred during reception [setting conditions] when the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 overrun error 0 reception in progress or completed [clearing conditions] after reading oer32 = 1, cleared by writing 0 to oer32 1 an overrun error has occurred during reception [setting conditions] when the next serial reception is completed with rdrf32 set to 1 multiprocessor bit receive multiprocessor bit transfer 0 data in which the multiprocessor bit is 0 has been received 1 data in which the multiprocessor bit is 1 has been received 0 a 0 multiprocessor bit is transmitted 1 a 1 multiprocessor bit is transmitted 3 per32 0 r/(w) ***** after reading tdre32 = 1, cleared by writing 0 to tdre32 when data is written to tdr32 by an instruction when bit te in serial control register 32 (scr32) is cleared to 0 when bit tdre32 is set to 1 when the last bit of a transmit character is sent when the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (pm32) in the serial mode register (smr32) 420 rdr32?eceive data register 32 h'ad sci32 bit initial value read/write 7 rdr327 0 r 6 rdr326 0 r 5 rdr325 0 r 4 rdr324 0 r 3 rdr323 0 r 0 rdr320 0 r 2 rdr322 0 r 1 rdr321 0 r tma?imer mode register a h'b0 timer a bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w internal clock select tma3 tma2 0 pss pss pss pss 0 4 1 clock output select 0 /32 /16 tma1 0 1 tma0 0 0 1 1 pss pss pss pss 10 1 0 0 1 1 1 psw psw psw psw 00 1 0 0 1 1 psw and tca are reset 10 1 0 0 1 1 prescaler and divider ratio or overflow period /8192 /4096 /2048 /512 /256 /128 /32 /8 1 s 0.5 s 0.25 s 0.03125 s interval timer time base (when using 32.768 khz) function 0 0 1 /8 /4 10 1 1 00 1 10 1 /32 w /16 w /8 w /4 w 3 tma3 0 r/w 421 tca?imer counter a h'b1 timer a bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value 422 tcsrw?imer control/status register w h'b2 watchdog timer bit initial value read/write 7 b6wi 1 r 6 tcwe 0 r/(w) 5 b4wi 1 r 4 tcsrwe 0 r/(w) 3 b2wi 1 r 0 wrst 0 r/(w) 2 wdon 0 r/(w) 1 b0wi 1 r ** * * watchdog timer reset 0 [clearing conditions] 1 [setting condition] when tcw overflows and a reset signal is generated reset by res pin when tcsrwe = 1, and 0 is written in both b0wi and wrst bit 0 write inhibit 0 bit 0 is write-enabled bit 0 is write-protected 1 watchdog timer on 0 watchdog timer operation is disabled watchdog timer operation is enabled 1 bit 2 write inhibit 0 bit 2 is write-enabled bit 2 is write-protected 1 timer control/status register w write enable 0 data cannot be written to bits 2 and 0 data can be written to bits 2 and 0 1 bit 4 write inhibit 0 bit 4 is write-enabled bit 4 is write-protected 1 timer counter w write enable 0 data cannot be written to tcw data can be written to tcw 1 bit 6 write inhibit 0 bit 6 is write-enabled bit 6 is write-protected 1 note: * write is permitted only under certain conditions. 423 tcw?imer counter w h'b3 watchdog timer bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 4 tcw4 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w count value tmc?imer mode register c h'b4 timer c bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 1 auto-reload function select clock select internal clock: internal clock: 0 1 internal clock: internal clock: 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 internal clock: internal clock: internal clock: external event (tmic): counting on rising or falling edge * : don t care /8192 /2048 /512 /64 /16 /4 w/4 0 interval timer function selected 1 auto-reload function selected counter up/down control 0 tcc is an up-counter 1 tcc is a down-counter * hardware control of tcc up/down operation by ud pin input ud pin input high: down-counter ud pin input low: up-counter 0 0 1 424 tcc?imer counter c h'b5 timer c bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r count value tlc?imer load register c h'b5 timer c bit initial value read/write 7 tlc7 0 r/w 6 tlc6 0 r/w 5 tlc5 0 r/w 4 tlc4 0 r/w 3 tlc3 0 r/w 0 tlc0 0 r/w 2 tlc2 0 r/w 1 tlc1 0 r/w reload value 425 tcrf?imer control register f h'b6 timer f b it i nitial value r ead/write 7 tolh 0 w 6 cksh2 0 w 5 cksh1 0 w 0 cksl0 0 w 2 cksl2 0 w 1 cksl1 0 w 4 cksh0 0 w clock select l 0 counting on external event (tmif) rising/falling edge internal clock /32 internal clock /16 internal clock /4 internal clock w/4 1 1 1 1 * 0 0 1 1 * 0 1 0 1 toggle output level l 0 low level 1 high level toggle output level h 0 low level 1 high level 3 toll 0 w clock select h 0 overflow signal internal clock /32 internal clock /16 internal clock /4 internal clock w/4 16-bit mode, counting on tcfl * : don t care 1 1 1 1 * 0 0 1 1 * 0 1 0 1 426 tcsrf?imer control/status register f h'b7 timer f b it i nitial value r ead/write note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. 7 ovfh 0 r/(w) 6 cmfh 0 r/(w) 5 ovieh 0 r/(w) 0 cclrl 0 r/w 2 cmfl 0 r/w 1 oviel 0 r/w 4 cclrh 0 r/(w) compare match flag h 0 clearing conditions: after reading cmfh = 1, cleared by writing 0 to cmfh 1 setting conditions: set when the tcfh value matches the ocrfh value timer overflow flag h 0 clearing conditions: after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting conditions: set when tcfh overflows from h'ff to h'00 compare match flag l 0 clearing conditions: after reading cmfl = 1, cleared by writing 0 to cmfl 1 setting conditions: set when the tcfl value matches the ocrfl value timer overflow flag l 0 clearing conditions: after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting conditions: set when tcfl overflows from h'ff to h'00 counter clear h 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled timer overflow interrupt enable h 0 tcfh overflow interrupt request is disabled 1 tcfh overflow interrupt request is enabled timer overflow interrupt enable l counter clear l 0 tcfl overflow interrupt request is disabled 1 tcfl overflow interrupt request is enabled 0 tcfl clearing by compare match is disabled 1 tcfl clearing by compare match is enabled 3 ovfl 0 r/(w) ** ** 427 tcfh?-bit timer counter fh h'b8 timer f bit initial value read/write 7 tcfh7 0 r/w 6 tcfh6 0 r/w 5 tcfh5 0 r/w 4 tcfh4 0 r/w 3 tcfh3 0 r/w 0 tcfh0 0 r/w 2 tcfh2 0 r/w 1 tcfh1 0 r/w count value tcfl?-bit timer counter fl h'b9 timer f bit initial value read/write 7 tcfl7 0 r/w 6 tcfl6 0 r/w 5 tcfl5 0 r/w 4 tcfl4 0 r/w 3 tcfl3 0 r/w 0 tcfl0 0 r/w 2 tcfl2 0 r/w 1 tcfl1 0 r/w count value ocrfh?utput compare register fh h'ba timer f bit initial value read/write 7 ocrfh7 1 r/w 6 ocrfh6 1 r/w 5 ocrfh5 1 r/w 4 ocrfh4 1 r/w 3 ocrfh3 1 r/w 0 ocrfh0 1 r/w 2 ocrfh2 1 r/w 1 ocrfh1 1 r/w ocrfl?utput compare register fl h'bb timer f bit initial value read/write 7 ocrfl7 1 r/w 6 ocrfl6 1 r/w 5 ocrfl5 1 r/w 4 ocrfl4 1 r/w 3 ocrfl3 1 r/w 0 ocrfl0 1 r/w 2 ocrfl2 1 r/w 1 ocrfl1 1 r/w 428 tmg?imer mode register g h'bc timer g bit initial value read/write 7 ovfh 0 r/(w) * 6 ovfl 0 r/(w) * 5 ovie 0 w 3 cclr1 0 w 0 cks0 0 w 2 cclr0 0 w 1 cks1 0 w 4 iiegs 0 w timer overflow flag h counter clear tcg clearing is disabled tcg cleared by falling edge of input capture input signal tcg cleared by rising edge of input capture input signal tcg cleared by both edges of input capture input signal 0 1 0 1 0 0 1 1 timer overflow interrupt enable tcg overflow interrupt request is disabled tcg overflow interrupt request is enabled 0 1 0 clearing conditions: after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting conditions: set when tcg overflows from h'ff to h'00 note: * bits 7 and 6 can only be written with 0, for flag clearing. timer overflow flag l 0 clearing conditions: after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting conditions: set when tcg overflows from h'ff to h'00 input capture interrupt edge select 0 interrupt generated on rising edge of input capture input signal 1 interrupt generated on falling edge of input capture input signal clock select 0 internal clock: counting on /64 0 internal clock: counting on /32 0 1 1 internal clock: counting on /2 1 internal clock: counting on w/4 0 1 429 icrgf?nput capture register gf h'bd timer g bit initial value read/write 7 icrgf7 0 r 6 icrgf6 0 r 5 icrgf5 0 r 4 icrgf4 0 r 3 icrgf3 0 r 0 icrgf0 0 r 2 icrgf2 0 r 1 icrgf1 0 r icrgr?nput capture register gr h'be timer g bit initial value read/write 7 icrgr7 0 r 6 icrgr6 0 r 5 icrgr5 0 r 4 icrgr4 0 r 3 icrgr3 0 r 0 icrgr0 0 r 2 icrgr2 0 r 1 icrgr1 0 r 430 lpcr?cd port control register h'c0 lcd controller/driver bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w 4 sgx 0 r/w clock enable bit 3 sgs3 0 0 0 0 0 1 0 * bit 4 sgx 0 1 bit 2 sgs2 0 0 0 1 1 * 0 * bit 1 sgs1 0 0 1 0 1 * 0 * bit 0 sgs0 0 1 * * * * 0 * function of pins seg 32 to seg 1 3 sgs3 0 r/w bit 4 sgx 0 pins seg 32 to seg 29 * (initial value) 1 pins cl 1 , cl 2 , do, m description port port seg seg seg seg port * seg 32 to seg 29 port port seg seg seg seg port seg 28 to seg 25 port port port seg seg seg port seg 24 to seg 21 port port port seg seg seg port use prohibited note: * seg32 to seg29 are external expansion pins. note: * these pins function as ports when the setting of sgs3 to sgs0 is 0000 or 0001. seg 20 to seg 17 port port port port seg seg port seg 16 to seg 13 port port port port seg seg port seg 12 to seg 9 port port port port port seg port seg 8 to seg 5 port port port port port seg port notes (initial value) seg 4 to seg 1 duty select, common function select bit 7 dts1 0 0 1 1 bit 6 dts0 0 1 0 1 bit 5 cmx 0 1 0 1 0 1 0 1 duty cycle static 1/2 duty 1/3 duty 1/4 duty common drivers com 1 com 4 to com 1 com 2 to com 1 com 4 to com 1 com 3 to com 1 com 4 to com 1 com 4 to com 1 com 4 to com 2 output the same waveform as com 1 com 4 outputs the same waveform as com 3 and com 2 outputs the same waveform as com 1 com 4 outputs a non-selected waveform notes * : don't care 431 lcr?cd control register h'c1 lcd controller/driver b it i nitial value r ead/write 7 1 6 psw 0 r/w 5 act 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 4 disp 0 r/w lcd drive power supply on/off control frame frequency select operating clock bit 1 bit 2 bit 3 0 0 0 1 1 1 1 1 1 1 1 * * * 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 * 0 1 0 1 0 1 0 1 bit 1 cks1 cks2 cks3 cks0 w w w/2 /2 /4 /8 /16 /32 /64 /128 /256 display function activate lcd controller/driver operation halted lcd controller/driver operates : don t care * 0 1 0 lcd drive power supply off 1 lcd drive power supply on display data control 0 blank data is displayed 1 lcd ram data is displayed 432 lcr2?cd control register 2 h'c2 lcd b it i nitial value r ead/write 7 lcdab 0 r/w 6 1 5 1 3 cds3 0 r/w 0 cds0 0 r/w 2 cds2 0 r/w 1 cds1 0 r/w 4 sups 0 r/w a waveform/b waveform switching control charge/discharge pulse duty cycle select duty cycle bit 1 bit 2 bit 3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 * * 0 1 0 1 0 1 0 1 * * 1 1/8 2/8 3/8 4/8 5/8 6/8 0 1/16 1/32 bit 1 cds1 cds2 cds3 cds0 : don t care * 0 drive using a waveform 1 drive using b waveform 5 v regulator control 0 applies to the h8/3867 series 1 5 v regulator halted 5 v regulator operates 433 amr?/d mode register h'c6 a/d converter b it i nitial value r ead/write 7 cks 0 r/w 6 trge 0 r/w 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select no channel selected bit 3 0 bit 2 analog input channel * : don t care ch3 ch2 0 ch1 ch0 bit 1 bit 0 0an 1 1 0 1 1 00 external trigger select 0 disables start of a/d conversion by external trigger 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg 5 1 4 an 5 an 6 an 7 ** 100 1 10 1 an 0 an 1 an 2 an 3 clock select 62/ bit 7 0 conversion period cks 31/ 1 62 s = 1 mhz 31 s 31 s = 2 mhz 15.5 s * conversion time n ote: * operation is not guaranteed with a conversion time of less than 15.5 s select a setting that gives a conversion time of at least 15.5 s. 434 adrrh?/d result register h h'c4 a/d converter adrrl?/d result register l h'c5 b it i nitial value r ead/write a drrh 7 adr9 not fixed r/(w) 6 adr8 not fixed r/(w) 5 adr7 not fixed r/(w) 3 adr5 not fixed r/(w) 0 adr2 not fixed r/(w) 2 adr4 not fixed r/(w) 1 adr3 not fixed r/(w) 4 adr6 not fixed r/(w) a/d conversion result b it i nitial value r ead/write a drrl 7 adr1 not fixed r 6 adr0 not fixed r 5 3 0 2 1 4 a/d conversion result adsr?/d start register h'c7 a/d converter bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 a/d status flag 0 1 read write read write indicates completion of a/d conversion stops a/d conversion indicates a/d conversion in progress starts a/d conversion 435 pmr1?ort mode register 1 h'c8 i/o port b it i nitial value r ead/write 7 irq3 0 r/(w) 6 irq2 0 r/(w) 5 irq1 0 r/(w) 3 tmig 0 r/(w) 0 tmow 0 r/(w) 2 tmofh 0 r/(w) 1 tmofl 0 r/(w) 4 irq4 0 r/(w) p1 0 /tmow pin function switch 0 functions as p1 0 i/o pin 1 functions as tmow output pin p1 2 /tmofh pin function switch 0 functions as p1 2 i/o pin 1 functions as tmofh output pin p1 3 /tmig pin function switch 0 functions as p1 3 i/o pin 1 functions as tmig input pin p1 4 /irq 4 /adtrg pin function switch 0 functions as p1 4 i/o pin 1 functions as irq 4 /adtrg input pin p1 5 /irq 1 /tmic pin function switch 0 functions as p1 5 i/o pin 1 functions as irq 1 /tmic input pin p1 1 /tmofl pin function switch 0 functions as p1 1 i/o pin 1 functions as tmofl output pin p1 6 /irq 2 pin function switch 0 functions as p1 6 i/o pin 1 functions as irq 2 input pin p1 7 /irq 3 /tmif pin function switch 0 functions as p1 7 i/o pin 1 functions as irq 3 /tmif input pin 436 pmr3?ort mode register 3 h'ca i/o port b it i nitial value r ead/write 7 aevl 0 r/(w) 6 aevh 0 r/(w) 5 wdcks 0 r/(w) 3 irq0 0 r/(w) 0 pwm 0 r/(w) 2 reso 0 r/(w) 1 ud 0 r/(w) 4 ncs 0 r/(w) p3 0 /pwm pin function switch 0 functions as p3 0 i/o pin 1 functions as pwm output pin p3 2 /reso pin function switch 0 functions as p3 2 i/o pin 1 functions as reso i/o pin p4 3 /irq0 pin function switch 0 functions as p4 3 i/o pin 1 functions as irq 0 input pin watchdog timer switch 0 8192 1 p3 1 /ud pin function switch 0 functions as p3 1 i/o pin 1 functions as ud input pin tmig noise canceler select 0 noise cancellation function not used 1 noise cancellation function used p3 6 /aevh pin function switch 0 functions as p3 6 i/o pin functions as aevh input pin w/4 1 p3 7 /aevl pin function switch 0 functions as p3 7 i/o pin 1 functions as aevl input pin 437 pmr5?ort mode register 5 h'cc i/o port pwcr?wm control register h'd0 14-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr0 0 w 2 1 1 pwcr1 0 w clock select 0 the input clock is /2 (t * = 2/ ) the conversion period is 16,384/ , with a minimum modulation width of 1/ the input clock is /4 (t * = 4/ ) the conversion period is 32,768/ , with a minimum modulation width of 2/ 1 the input clock is /8 (t * = 8/ ) the conversion period is 65,536/ , with a minimum modulation width of 4/ the input clock is /16 (t * = 16/ ) the conversion period is 131,072/ , with a minimum modulation width of 8/ note: t : period of pwm input clock * 438 pwdru?wm data register u h'd1 14-bit pwm bit initial value read/write 7 1 6 1 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w upper 6 bits of data for generating pwm waveform pwdru5 pwdru4 pwdru3 pwdru0 pwdru2 pwdur1 pwdrl?wm data register l h'd2 14-bit pwm bit initial value read/write 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w lower 8 bits of data for generating pwm waveform pwdrl5 pwdrl4 pwdrl3 pwdrl0 pwdrl2 pwdrl1 pwdrl6 pwdrl7 pdr1?ort data register 1 h'd4 i/o ports bit initial value read/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 7 6543210 pdr3?ort data register 3 h'd6 i/o ports bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 r/w 2 p3 0 r/w 1 p3 0 r/w 0 2 3 4 5 6 7 1 pdr4?ort data register 4 h'd7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 30 21 439 pdr5?ort data register 5 h'd8 i/o ports bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 30 21 4 5 6 7 pdr6?ort data register 6 h'd9 i/o ports bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 30 21 4 5 6 7 pdr7?ort data register 7 h'da i/o ports bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 3210 4 5 6 7 pdr8?ort data register 8 h'db i/o ports bit initial value read/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 30 21 4 5 6 7 pdra?ort data register a h'dd i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 30 21 440 pdrb?ort data register b h'de i/o ports bit initial value read/write 7 pb r 6 pb r 5 pb r 4 pb r 3 pb r 0 pb r 2 pb r 1 pb r 30 21 4 5 6 7 pucr1?ort pull-up control register 1 h'e0 i/o ports bit initial value read/write 7 pucr1 0 r/w 6 pucr1 0 r/w 5 pucr1 0 r/w 4 pucr1 0 r/w 3 pucr1 0 r/w 0 pucr1 0 r/w 2 pucr1 0 r/w 1 pucr1 0 r/w 0 43 21 5 6 7 pucr3?ort pull-up control register 3 h'e1 i/o ports bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 0 2 3 4 5 6 7 1 pucr5?ort pull-up control register 5 h'e2 i/o ports bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 30 21 4 5 6 7 pucr6?ort pull-up control register 6 h'e3 i/o ports bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 30 21 4 5 6 7 441 pcr1?ort control register 1 h'e4 i/o ports bit initial value read/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w port 1 input/output select 0 input pin 1 output pin 7 6543210 pcr3?ort control register 3 h'e6 i/o ports bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w port 3 input/output select 0 input pin 1 output pin 0 2 3 4 5 6 7 1 pcr4?ort control register 4 h'e7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w port 4 input/output select 0 input pin 1 output pin 0 21 442 pcr5?ort control register 5 h'e8 i/o ports bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w port 5 input/output select 0 input pin 1 output pin 76543 0 21 pcr6?ort control register 6 h'e9 i/o ports bit initial value read/write 7 pcr6 0 w 6 pcr6 0 w 5 pcr6 0 w 4 pcr6 0 w 3 pcr6 0 w 0 pcr6 0 w 2 pcr6 0 w 1 pcr6 0 w port 6 input/output select 0 input pin 1 output pin 76543 0 21 pcr7?ort control register 7 h'ea i/o ports bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w port 7 input/output select 0 input pin 1 output pin 7 65 432 10 443 pcr8?ort control register 8 h'eb i/o ports bit initial value read/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w port 8 input/output select 0 input pin 1 output pin 76543 0 21 pcra?ort control register a h'ed i/o ports bit initial value read/write 7 0 6 0 5 0 4 0 3 pcra 0 r/w 0 pcra 0 r/w 2 pcra 0 r/w 1 pcra 0 r/w 0 1 2 3 port a input/output select 0 input pin 1 output pin 444 syscr1?ystem control register 1 h'f0 system control b it i nitial value r ead/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 1 1 ma1 1 r/w 4 sts0 0 r/w software standby 0 when a sleep instruction is executed in active mode, a transition is made to sleep mode 1 standby timer select 2 to 0 0 wait time = 8,192 states wait time = 16,384 states 0 0 1 wait time = 32,768 states wait time = 65,536 states 10 1 active (medium-speed) mode clock select /16 /32 0 1 0 0 1 1 /64 /128 1 1 00 10 1 wait time = 131,072 states wait time = 2 states wait time = 8 states wait time = 16 states low speed on flag 0 the cpu operates on the system clock ( ) 1 the cpu operates on the subclock ( ) sub when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode when a sleep instruction is executed in subactive mode, a transition is made to watch mode osc osc osc osc 445 syscr2?ystem control register 2 h'f1 system control b it i nitial value r ead/write 7 1 6 1 5 1 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 4 nesel 1 r/w subactive mode clock select 0 /8 /4 0 1 1 /2 * w w w direct transfer on flag 0 when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode 1 when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 medium speed on flag 0 operates in active (high-speed) mode 1 operates in active (medium-speed) mode noise elimination sampling frequency select 0 sampling rate is /16 1 sampling rate is /4 osc osc * : don t care 446 iegr?rq edge select register h'f2 system control bit initial value read/write 7 0 6 1 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w 5 1 irq 0 edge select 0 falling edge of irq 0 pin input is detected rising edge of irq 0 pin input is detected 1 irq 1 edge select 0 falling edge of irq 1 , tmic pin input is detected rising edge of irq 1 , tmic pin input is detected 1 irq 2 edge select 0 falling edge of irq 2 pin input is detected rising edge of irq 2 pin input is detected 1 irq 3 edge select 0 falling edge of irq 3 , tmif pin input is detected rising edge of irq 3 , tmif pin input is detected 1 irq 4 edge select 0 falling edge of irq 4 pin and adtrg pin is detected 3. rising edge of irq 4 pin and adtrg pin is detected 1 447 ienr1?nterrupt enable register 1 h'f3 system control bit initial value read/write 7 ienta 0 r/w 6 0 r/w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w 5 ienwp 0 r/w irq 4 to irq 0 interrupt enable 0 disables irq 4 to irq 0 interrupt requests enables irq 4 to irq 0 interrupt requests 1 wakeup interrupt enable 0 disables wkp 7 to wkp 0 interrupt requests enables wkp 7 to wkp 0 interrupt requests 1 timer a interrupt enable 0 disables timer a interrupt requests enables timer a interrupt requests 1 448 ienr2?nterrupt enable register 2 h'f4 system control bit initial value read/write 7 iendt 0 r/(w) 6 ienad 0 r/(w) 5 0 r/w 3 ientfh 0 r/(w) 0 ienec 0 r/(w) 2 ientfl 0 r/(w) 1 ientc 0 r/(w) 4 ientg 0 r/(w) asynchronous event counter interrupt enable 0 disables asynchronous event counter interrupt requests 1 enables asynchronous event counter interrupt requests timer fl interrupt enable 0 disables timer fl interrupt requests 1 enables timer fl interrupt requests timer fh interrupt enable 0 disables timer fh interrupt requests 1 enables timer fh interrupt requests timer g interrupt enable 0 disables timer g interrupt requests 1 enables timer g interrupt requests a/d converter interrupt enable 0 disables a/d converter interrupt requests 1 enables a/d converter interrupt requests timer c interrupt enable 0 disables timer c interrupt requests 1 enables timer c interrupt requests direct transition interrupt enable 0 disables direct transition interrupt requests 1 enables direct transition interrupt requests 449 irr1?nterrupt request register 1 h'f6 system control b it i nitial value r ead/write 7 irrta 0 r/w * 6 0 r/w 5 1 3 irri3 0 r/w * 0 irri0 0 r/w * 2 irri2 0 r/w * 1 irri1 0 r/w * 4 irri4 0 r/w * irq4 to irq0 interrupt request flags 0 clearing conditions: when irrin = 1, it is cleared by writing 0 (n = 4 to 0) note: * bits 7 and 4 to 0 can only be written with 0, for flag clearing. 1 setting conditions: when pin irqn is designated for interrupt input and the designated signal edge is input timer a interrupt request flag 0 clearing conditions: when irrta = 1, it is cleared by writing 0 1 setting conditions: when the timer a counter value overflows (rom h'ff to h'00) 450 irr2?nterrupt request register 2 h'f7 system control bit initial value read/write 7 irrdt 0 r/(w) * 6 irrad 0 r/(w) * 5 0 r/w 3 irrtfh 0 r/(w) * 0 irrec 0 r/(w) * 2 irrtfl 0 r/(w) * 1 irrtc 0 r/(w) * 4 irrtg 0 r/(w) * timer g interrupt request flag timer c interrupt request flag 0 clearing conditions: when irrtg = 1, it is cleared by writing 0 1 setting conditions: when the tmig pin is designated for tmig input and the designated signal edge is input note: * bits 7, 6 and 4 to 0 can only be written with 0, for flag clearing. a/d converter interrupt request flag 0 clearing conditions: when irrad = 1, it is cleared by writing 0 1 setting conditions: when the a/d converter completes conversion and adsf is reset direct transition interrupt request flag 0 clearing conditions: when irrdt = 1, it is cleared by writing 0 1 setting conditions: when a sleep instruction is executed while dton is set to 1, and a direct transition is made timer fh interrupt request flag 0 clearing conditions: when irrtfh = 1, it is cleared by writing 0 1 setting conditions: when counter fh and output compare register fh match in 8-bit timer mode, or when 16-bit counters fl and fh and output compare registers fl and fh match in 16-bit timer mode timer fl interrupt request flag 0 clearing conditions: when irrtfl = 1, it is cleared by writing 0 1 setting conditions: when counter fl and output compare register fl match in 8-bit timer mode asynchronous event counter interrupt request flag 0 clearing conditions: when irrec = 1, it is cleared by writing 0 1 setting conditions: when the asynchronous event counter value overflows 0 clearing conditions: when irrtc = 1, it is cleared by writing 0 1 setting conditions: when the timer c counter value overflows (from h'ff to h'00) or underflows (from h'00 to h'ff) 451 iwpr?akeup interrupt request register h'f9 system control b it i nitial value r ead/write 7 iwpf7 0 r/(w) * 6 iwpf6 0 r/(w) * 5 iwpf5 0 r/(w) * 3 iwpf3 0 r/(w) * 0 iwpf0 0 r/(w) * 2 iwpf2 0 r/(w) * 1 iwpf1 0 r/(w) * 4 iwpf4 0 r/(w) * 0 clearing conditions: when iwpfn = 1, it is cleared by writing 0 (n = 7 to 0) note: * all bits can only be written with 0, for flag clearing. wakeup interrupt request register 1 setting conditions: when pin wkpn is designated for wakeup input and a falling edge is input at that pin 452 ckstpr1?lock stop register 1 h'fa system control b it i nitial value r ead/write 7 1 r/w 6 s31ckstp 1 r/w 5 s32ckstp 1 r/w 3 tgckstp 1 r/w 0 tackstp 1 r/w 2 tfckstp 1 r/w 1 tcckstp 1 r/w 4 adckstp 1 r/w timer a module standby mode control timer f module standby mode control 0 timer f is set to module standby mode timer f module standby mode is cleared 1 timer g interrupt enable 0 timer g is set to module standby mode timer g module standby mode is cleared 1 a/d converter module standby mode control 0 a/d converter is set to module standby mode a/d converter module standby mode is cleared 1 timer c module standby mode control 0 timer c is set to module standby mode timer c module standby mode is cleared 1 0 timer a is set to module standby mode timer a module standby mode is cleared 1 sci3-2 module standby mode control 0 sci3-2 is set to module standby mode sci3-2 module standby mode is cleared 1 sci3-1 module standby mode control 0 sci3-1 is set to module standby mode sci3-1 module standby mode is cleared 1 453 ckstpr2?lock stop register 2 h'fb system control b it i nitial value r ead/write 7 1 6 1 5 1 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 wdckstp 1 r/w 1 pwckstp 1 r/w 4 1 lcd module standby mode control wdt module standby mode control 0 wdt is set to module standby mode wdt module standby mode is cleared 1 asynchronous event counter module standby mode control 0 asynchronous event counter is set to module standby mode asynchronous event counter module standby mode is cleared 1 pwm module standby mode control 0 pwm is set to module standby mode pwm module standby mode is cleared 1 0 lcd is set to module standby mode lcd module standby mode is cleared 1 454 appendix c i/o port block diagrams c.1 block diagrams of port 1 v cc v cc v ss pucr1 n pmr1 n pdr1 n pcr1 n irq n? sby (low level during reset and in standby mode) internal data bus pdr1: pcr1: pmr1: pucr1: n = 7 to 4 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 p1 n figure c.1 (a) port 1 block diagram (pins p1 7 to p1 4 ) 455 v cc v cc sby v ss pucr1 3 pmr1 3 pdr1 3 pcr1 3 timer g module tmig internal data bus p1 3 figure c.1 (b) port 1 block diagram (pin p1 3 ) v cc v cc v ss pucr1 n pmr1 n pdr1 n pcr1 n sby internal data bus pdr1: pcr1: pmr1: pucr1: n= 2, 1 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmofh (p1 2 ) tmofl (p1 1 ) timer f module p1 n figure c.1 (c) port 1 block diagram (pin p1 2 , p1 1 ) 456 v cc v cc v ss pucr1 0 pmr1 0 pdr1 0 pcr1 0 sby internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmow timer a module p1 0 figure c.1 (d) port 1 block diagram (pin p1 0 ) 457 c.2 block diagrams of port 3 p3 n v cc v cc pucr3 n pmr3 n pdr3 n pcr3 n aec module internal data bus sby v ss aevh(p3 6 ) aevl(p3 7 ) pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 n=7 to 6 figure c.2 (a) port 3 block diagram (pin p3 7 to p3 6 ) 458 p3 5 sci31 module pdr3 5 pucr3 scinv1 spc31 pcr3 5 sby v ss pdr3: port data register 3 pcr3: port control register 3 txd31 internal data bus v cc v cc figure c.2 (b) port 3 block diagram (pin p3 5 ) 459 p3 4 v cc v cc sci31 module pdr3 4 pcr3 4 scinv0 sby v ss pdr3: port data register 3 pcr3: port control register 3 re31 rxd31 internal data bus pucr3 figure c.2 (c) port 3 block diagram (pin p3 4 ) 460 p3 3 v cc sci31 module pdr3 3 pcr3 3 sby v ss pdr3: port data register 3 pcr3: port control register 3 sckie31 sckoe31 scko31 scki31 internal data bus pucr3 v cc figure c.2 (d) port 3 block diagram (pin p3 3 ) 461 p3 2 v cc v cc pucr3 2 internal data bus pmr3 2 pdr3 2 pcr3 2 sby v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 reso figure c.2 (e) port 3 block diagram (pin p3 2 ) 462 v cc v cc v ss pucr3 1 pdr3 1 pcr3 1 ud sby internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 p3 1 timer c module pmr3 1 figure c.2 (f) port 3 block diagram (pin p3 1 ) 463 p3 0 v cc v cc pucr3 0 pmr3 0 pdr3 0 pcr3 0 sby v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 pwm pwm module internal data bus figure c.2 (g) port 3 block diagram (pin p3 0 ) 464 c.3 block diagrams of port 4 p4 3 pmr4 3 internal data bus irq 0 pmr4: port mode register 4 figure c.3 (a) port 4 block diagram (pin p4 3 ) 465 p4 2 sci32 module internal data bus pdr4 2 scinv3 pcr4 2 sby v ss pdr4: port data register 4 pcr4: port control register 4 txd32 v cc spc32 figure c.3 (b) port 4 block diagram (pin p4 2 ) 466 p4 1 v cc sci32 module pdr4 1 pcr4 1 sby v ss pdr4: port data register 4 pcr4: port control register 4 re32 rxd32 internal data bus scinv2 figure c.3 (c) port 4 block diagram (pin p4 1 ) 467 p4 0 v cc sci32 module pdr4 0 pcr4 0 sby v ss pdr4: port data register 4 pcr4: port control register 4 sckie32 sckoe32 scko32 internal data bus scki32 figure c.3 (d) port 4 block diagram (pin p4 0 ) 468 c.4 block diagram of port 5 p5 n v cc v cc pucr5 n internal data bus pmr5 n pdr5 n pcr5 n sby v ss wkp n pdr5: port data register 5 pcr5: port control register 5 pmr5: port mode register 5 pucr5: port pull-up control register 5 n = 7 to 0 figure c.4 port 5 block diagram 469 c.5 block diagram of port 6 p6 n v cc v cc pucr6 n pdr6 n internal data bus pcr6 n sby v ss pdr6: port data register 6 pcr6: port control register 6 pucr6: port pull-up control register 6 n = 7 to 0 figure c.5 port 6 block diagram 470 c.6 block diagram of port 7 p7 n v cc pdr7 n internal data bus pcr7 n sby v ss pdr7: port data register 7 pcr7: port control register 7 n = 7 to 0 figure c.6 port 7 block diagram 471 c.7 block diagrams of port 8 p8 n v cc pdr8 n internal data bus pcr8 n sby v ss pdr8: pcr8: n= 7 to 0 port data register 8 port control register 8 figure c.7 port 8 block diagram 472 c.8 block diagram of port a pa n v cc pdra n internal data bus pcra n sby v ss pdra: port data register a pcra: port control register a n = 3 to 0 figure c.8 port a block diagram 473 c.9 block diagram of port b pb n internal data bus amr3 to amr0 a/d module v in n = 7 to 0 dec figure c.9 port b block diagram 474 appendix d port states in the different processing states table d.1 port states overview port reset sleep subsleep standby watch subactive active p1 7 to p1 0 high impedance retained retained high impedance * 1 retained functions functions p3 7 to p3 0 high impedance * 2 retained retained high impedance * 1 retained functions functions p4 3 to p4 0 high impedance retained retained high impedance retained functions functions p5 7 to p5 0 high impedance retained retained high impedance * 1 retained functions functions p6 7 to p6 0 high impedance retained retained high impedance retained functions functions p7 7 to p7 0 high impedance retained retained high impedance retained functions functions p8 7 to p8 0 high impedance retained retained high impedance retained functions functions pa 3 to pa 0 high impedance retained retained high impedance retained functions functions pb 7 to pb 0 high impedance high impedance high impedance high impedance high impedance high impedance high impedance notes: 1. high level output when mos pull-up is in on state. 2. p3 2 is functions 475 appendix e list of product codes table e.1 h8/3864 series product code lineup product type product code mark code package (hitachi package code) h8/3867 h8/3862 mask rom hd6433862h hd6433862( *** )h 80 pin qfp (fp-80a) series versions hd6433862f hd6433862( *** )f 80-pin qfp (fp-80b) hd6433862w hd6433862( *** )w 80-pin tqfp (tfp-80c) h8/3863 mask rom hd6433863h hd6433863( *** )h 80-pin qfp (fp-80a) versions hd6433863f hd6433863( *** )f 80-pin qfp (fp-80b) hd6433863w hd6433863( *** )w 80-pin tqfp (tfp-80c) h8/3864 mask rom hd6433864h hd6433864( *** )h 80-pin qfp (fp-80a) versions hd6433864f hd6433864( *** )f 80-pin qfp (fp-80b) hd6433864w hd6433864( *** )w 80-pin tqfp (tfp-80c) h8/3865 mask rom hd6433865h hd6433865( *** )h 80-pin qfp (fp-80a) versions hd6433865f hd6433865( *** )f 80-pin qfp (fp-80b) hd6433865w hd6433865( *** )w 80-pin tqfp (tfp-80c) h8/3866 mask rom HD6433866h HD6433866( *** )h 80-pin qfp (fp-80a) versions HD6433866f HD6433866( *** )f 80-pin qfp (fp-80b) HD6433866w HD6433866( *** )w 80-pin tqfp (tfp-80c) h8/3867 mask rom hd6433867h hd6433867( *** )h 80-pin qfp (fp-80a) versions hd6433867f hd6433867( *** )f 80-pin qfp (fp-80b) hd6433867w hd6433867( *** )w 80-pin tqfp (tfp-80c) ztat hd6473867h hd6473867h 80-pin qfp (fp-80a) versions hd6473867f hd6473867f 80-pin qfp (fp-80b) hd6473867w hd6473867w 80-pin tqfp (tfp-80c) note: for mask rom versions, ( *** ) is the rom code. 476 table e.1 h8/3864 series product code lineup (cont) product type product code mark code package (hitachi package code) h8/3827 h8/3822 mask rom hd6433822h hd6433822( *** )h 80-pin qfp (fp-80a) series versions hd6433822f hd6433822( *** )f 80-pin qfp (fp-80b) hd6433822w hd6433822( *** )w 80-pin tqfp (tfp-80c) h8/3823 mask rom hd6433823h hd6433823( *** )h 80-pin qfp (fp-80a) versions hd6433823f hd6433823( *** )f 80-pin qfp (fp-80b) hd6433823w hd6433823( *** )w 80-pin tqfp (tfp-80c) h8/3824 mask rom hd6433824h hd6433824( *** )h 80-pin qfp (fp-80a) versions hd6433824f hd6433824( *** )f 80-pin qfp (fp-80b) hd6433824w hd6433824( *** )w 80-pin tqfp (tfp-80c) h8/3825 mask rom hd6433825h hd6433825( *** )h 80-pin qfp (fp-80a) versions hd6433825f hd6433825( *** )f 80-pin qfp (fp-80b) hd6433825w hd6433825( *** )w 80-pin tqfp (tfp-80c) h8/3826 mask rom hd6433826h hd6433826( *** )h 80-pin qfp (fp-80a) versions hd6433826f hd6433826( *** )f 80-pin qfp (fp-80b) hd6433826w hd6433826( *** )w 80-pin tqfp (tfp-80c) h8/3827 mask rom hd6433827h hd6433827( *** )h 80-pin qfp (fp-80a) versions hd6433827f hd6433827( *** )f 80-pin qfp (fp-80b) hd6433827w hd6433827( *** )w 80-pin tqfp (tfp-80c) ztat hd6473827h hd6473827h 80-pin qfp (fp-80a) versions hd6473827f hd6473827f 80-pin qfp (fp-80b) hd6473827w hd6473827w 80-pin tqfp (tfp-80c) note: for mask rom versions, ( *** ) is the rom code. 477 appendix f package dimensions dimensional drawings of h8/3867 and h8/3827 series packages fp-80a, fp-80b and tfp-80c are shown in figures f.1, f.2 and f.3 below. hitachi code jedec eiaj weight (reference value) fp-80a conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 60 0 ?8 0.10 0.12 m 17.2 0.3 41 61 80 1 20 40 21 17.2 0.3 *0.32 0.08 0.65 3.05 max 1.6 0.8 0.3 14 2.70 *0.17 0.05 0.10 +0.15 ?.10 0.83 0.30 0.06 0.15 0.04 figure f.1 fp-80a package dimensions 478 hitachi code jedec eiaj weight (reference value) fp-80b 1.7 g unit: mm *dimension including the plating thickness base material dimension 0.15 m 0 10 *0.37 0.08 *0.17 0.05 3.10 max 1.2 0.2 24.8 0.4 20 64 41 40 25 24 1 80 65 18.8 0.4 14 0.15 0.8 2.70 2.4 0.20 +0.10 0.20 0.8 1.0 0.35 0.06 0.15 0.04 figure f.2 fp-80b package dimensions 479 hitachi code jedec eiaj weight (reference value) tfp-80c conforms 0.4 g unit: mm *dimension including the plating thickness base material dimension 0.10 m 0.10 0.5 0.1 0 8 1.20 max 14.0 0.2 0.5 12 14.0 0.2 60 41 120 80 61 21 40 *0.17 0.05 1.0 *0.22 0.05 0.10 0.10 1.00 1.25 0.20 0.04 0.15 0.04 figure f.3 tfp-80c package dimensions h8/3867 series, h8/3827 series hardware manual publication date: 1st edition, november 1997 3rd edition, february 1999 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group ul media co., ltd. copyright ? hitachi, ltd., 1997. all rights reserved. printed in japan. |
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